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Zener diode manufacturing method based on CMOS manufacturing process

A manufacturing method and manufacturing process technology, applied in the field of Zener tube manufacturing, can solve the problems of uneven distribution of Zener implanted impurity concentration, uneven breakdown voltage, etc.

Active Publication Date: 2016-10-19
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In order to solve at least one of the problems mentioned in the background art that the concentration distribution of zener implanted impurities is uneven, the breakdown voltage of zener breakdown is unstable, and the leakage current before zener breakdown is too large and uneven, etc., this paper The invention provides a method for manufacturing a Zener tube based on a CMOS manufacturing process

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  • Zener diode manufacturing method based on CMOS manufacturing process
  • Zener diode manufacturing method based on CMOS manufacturing process
  • Zener diode manufacturing method based on CMOS manufacturing process

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Embodiment Construction

[0029] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of ...

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Abstract

The invention provides a Zener diode manufacturing method based on a CMOS manufacturing process. A polysilicon deposition process, a Zener implanting process, a sidewall dielectric layer deposition process, a sidewall dielectric layer etching process and a source / drain implanting process are successively performed. The traditional Zener implanting process is performed before the sidewall dielectric layer deposition process, the sidewall dielectric layer etching process and the source / drain implanting process, thereby preventing substrate damage by the sidewall dielectric layer etching process and substrate damage in formation of amorphous structures which may caused by the source / drain implanting process, so that concentration distribution uniformity of impurities which are implanted into the Zener diode is improved, thereby obtaining a stable breakdown voltage in breakdown of the Zener diode, preventing defects of large leakage current and low uniformity of the leakage current before breakdown of the Zener diode, and improving market competitiveness of the product.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a method for manufacturing a Zener tube based on a CMOS manufacturing process. Background technique [0002] To manufacture a Zener diode, a traditional method requires the application of a CMOS (Complementary Metal Oxide Semiconductor) process: a polysilicon deposition process, a polysilicon etching process (Poly Etch), and a sidewall dielectric Layer deposition process and side wall dielectric layer etching process (Spacer Etch), drain source implantation process (Source / Drain Imp), and Zener implantation process (Zener Imp). In this traditional method, the Zener implantation process is placed behind the source-drain implantation process. At this time, the substrate surface has been damaged by the sidewall dielectric layer etching process, and the higher implant dose of the source-drain implantation process has There is a great chance to cause damage to the subst...

Claims

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Application Information

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IPC IPC(8): H01L21/329H01L21/266
CPCH01L21/266H01L29/66106
Inventor 李春旭
Owner CSMC TECH FAB2 CO LTD
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