Super junction structure and manufacturing method thereof

A technology of superjunction and unit structure, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as affecting device consistency, device performance deviation, and increasing the difficulty of process control.

Active Publication Date: 2020-06-26
SHENZHEN SANRISE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But in this way, the concentration of P-type impurities will be selected to be higher than the concentration of N-type impurities to achieve charge balance. This increases the difficulty of process control in the manufacturing process, especially in the trench process, because process control is generally based on The offset percentage of the center line is controlled. For example, the resistivity changes within plus or minus 3%, so that the absolute value of the concentration increases, and the same percentage of process changes will increase the change in the total amount of impurities and the degree of charge imbalance. It is serious, and the deviation of device performance, including the deviation of breakdown voltage, is large, which affects the consistency of the device

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  • Super junction structure and manufacturing method thereof

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no. 1 example

[0075] The super junction structure of the first embodiment of the present invention:

[0076] Such as Figure 1C Shown is the device structure diagram of the super junction structure of the first embodiment of the present invention; figure 2 It is a device structure diagram of a super-junction device formed by adopting the super-junction structure of the first embodiment of the present invention. The super-junction structure of the first embodiment of the present invention includes:

[0077] The first N-type sub-epitaxial layer 2 is formed in the first N-type sub-epitaxial layer 2 with first P-type sub-columns 31 and first N-type sub-columns 21 alternately arranged to form a first super-junction sub-structure.

[0078] The second N-type sub-epitaxial layer is formed on the surface of the first N-type sub-epitaxial layer 2 formed with the first superjunction sub-structure, and the second N-type sub-epitaxial layer is formed in the second N-type sub-epitaxial layer. The seco...

no. 1 example

[0109] for more clarity figure 2 The super junction device of the first embodiment of the present invention is shown, and the device structure of the first embodiment of the present invention will be described below with specific parameters:

[0110] The device in the first embodiment of the present invention is an N-type super-junction MOSFET, the resistivity of the semiconductor substrate 11 is 0.001 ohm·cm-0.003 ohm·cm, and the thickness is about 725 microns.

[0111] The position of the bottom surface of the first sub-trench 102a is shown by the line A1A2, and the position of the top surface of the first sub-trench 102a is shown by the line B1B2.

[0112] refer to Figure 1C As shown, the thickness of the first N-type sub-epitaxial layer 2 is 30 microns; the side slope angle of the first sub-trench 102a is 88.6 degrees, and the side slope angle of the first sub-trench 102a corresponds to the The angle between the side surface and the bottom surface of the first N-shaped...

no. 4 example

[0152] The superjunction structure of the fourth embodiment of the present invention:

[0153] The difference between the super junction structure of the fourth embodiment of the present invention and the super junction structure of the first embodiment of the present invention is, for example Figure 7A Shown is a device structure diagram of a super-junction device formed by using the super-junction structure of the fourth embodiment of the present invention. The super-junction structure of the fourth embodiment of the present invention includes the following features:

[0154]The second sub-groove 102b is a groove whose top opening is larger than the bottom opening and the sides are inclined, the sides of the first sub-groove 102a are vertical, and the width of the first sub-groove 102a is equal to that of the second sub-groove. By the width of the bottom opening of the groove 102b, the bottom surface of the second sub-trench 102b is aligned with the top surface of the first...

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Abstract

The invention discloses a super junction structure, and the structure is formed by superposing two layers of super junction substructures, wherein the two layers of P-type subcolumns are both composedof P-type sub epitaxial layers filled in corresponding sub grooves, the width of the P-type column at the top of each subcolumn is larger than that of the N-type column, and the doping concentrationof the P-type columns can be reduced while the doping concentration of the N-type columns is improved. Charge balance between the P-type column and the N-type column is set according to the fact thatonly one longitudinal position in the whole super-junction unit structure has the maximum electric field intensity when the device is reversely biased. The invention further discloses a manufacturingmethod of the super junction structure. According to the invention, the consistency of device performances such as breakdown voltage and avalanche tolerance can be improved; meanwhile, the on resistance of the device is kept or reduced, and high-temperature application of the device is facilitated.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction structure; the invention also relates to a manufacturing method of the super junction structure. Background technique [0002] The super junction structure is a structure of alternately arranged N-type pillars and P-type pillars. If the superjunction structure is used to replace the N-type drift region in the vertical double-diffused MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device, a conduction path is provided in the conduction state. For N-type devices, only N The P-type column provides a path, but the P-type column does not provide it; in the off state, it bears the reverse bias voltage. At this time, the P-type column and the N-type column deplete each other laterally and bear together, forming a super junction metal-oxide semiconductor field effect transistor. (Metal-Oxide-Semiconductor Field-Ef...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/78H01L21/336
CPCH01L29/0634H01L29/7813H01L29/66734
Inventor 肖胜安
Owner SHENZHEN SANRISE TECH CO LTD
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