Manufacturing method of zener tube based on cmos manufacturing process

A manufacturing method and manufacturing process technology, applied in the field of Zener tube manufacturing, can solve the problems of uneven distribution of Zener implanted impurity concentration, unstable and uneven breakdown voltage, etc.

Active Publication Date: 2020-02-18
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In order to solve at least one of the problems mentioned in the background art that the concentration distribution of zener implanted impurities is uneven, the breakdown voltage of zener breakdown is unstable, and the leakage current before zener breakdown is too large and uneven, etc., this paper The invention provides a method for manufacturing a Zener tube based on a CMOS manufacturing process

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  • Manufacturing method of zener tube based on cmos manufacturing process
  • Manufacturing method of zener tube based on cmos manufacturing process
  • Manufacturing method of zener tube based on cmos manufacturing process

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Embodiment Construction

[0029] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or mor...

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Abstract

The invention provides a Zener diode manufacturing method based on a CMOS manufacturing process. A polysilicon deposition process, a Zener implanting process, a sidewall dielectric layer deposition process, a sidewall dielectric layer etching process and a source / drain implanting process are successively performed. The traditional Zener implanting process is performed before the sidewall dielectric layer deposition process, the sidewall dielectric layer etching process and the source / drain implanting process, thereby preventing substrate damage by the sidewall dielectric layer etching process and substrate damage in formation of amorphous structures which may caused by the source / drain implanting process, so that concentration distribution uniformity of impurities which are implanted into the Zener diode is improved, thereby obtaining a stable breakdown voltage in breakdown of the Zener diode, preventing defects of large leakage current and low uniformity of the leakage current before breakdown of the Zener diode, and improving market competitiveness of the product.

Description

Technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a method for manufacturing a Zener tube based on a CMOS manufacturing process. Background technique [0002] To manufacture Zener diodes, a traditional method requires the application of CMOS (Complementary Metal Oxide Semiconductor) process: polysilicon deposition process, polysilicon etching process (Poly Etch), and sidewall dielectric Layer deposition process, sidewall dielectric layer etching process (SpacerEtch), drain-source implant process (Source / Drain Imp), Zener implant process (Zener Imp). In this traditional approach, the Zener implantation process is placed after the source-drain implantation process. At this time, the substrate surface has been damaged by the sidewall dielectric layer etching process, and the source-drain implantation process has a higher implant dose. There is a great chance of causing damage to the surface of the substrate, causing the o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/329H01L21/266
CPCH01L21/266H01L29/66106
Inventor 李春旭
Owner CSMC TECH FAB2 CO LTD
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