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A processing space contains an array of operational transistors interconnected by circuit and signal pass transistors that when supplied with selected enable bits will structure a variety of circuits that will carry out any desired information processing. The Babbage / von Neumann Paradigm in which data are provided to circuitry that would operate on those data is reversed by structuring the desired circuits at the site(s) of the data, thereby to eliminate the von Neumann bottleneck and substantially increase the computing power of the device, with the apparatus conducting only non-stop Information Processing on a steady stream of data and code, with no repetitious Instruction and data transfers as in the normal computer being required. A code is defined that will identify the physical locations of every transistor in the processing space, which code will then enable only selected ones of the pass transistors therein so as to structure the circuits needed for any algorithm sought to be executed. The circuits so structured, operating independently of and in parallel with every other circuit so structured, are then restructured after each step into another group of circuits, so that almost no transistor will ever “sit idle,” but all of the processing space can be devoted entirely to information processing, thereby again to increase enormously the computing power of the device. The apparatus is also super-scalable, meaning that an Instant Logic Apparatus built around that processing space could be built to have any size, speed, and level of computer power desired.