34results about How to "Will not increase the difficulty of the process" patented technology

The invention relates to a metasurface-based uncooled infrared imaging sensor, which comprises a double-layer uncooled infrared detector. The double-layer uncooled infrared detector comprises a semiconductor substrate and a detector body; the detector body comprises a first suspended structure layer and a second suspended structure layer; the first suspended structure layer comprises a metal reflective layer, an insulating dielectric layer, a metal electrode layer, an electrode protective layer, a first supporting layer, a heat sensitive protective layer and a heat sensitive layer; the secondsuspended structure layer comprises a metamaterial support layer and a metamaterial support protective layer; a metamaterial structure is arranged on the metamaterial support protective layer; and themetamaterial structure adopts NiCr or / and Al, and the thickness is between 12 to 30 nm. The preparation process is simple and is compatible with a CMOS process, and functions of multi-color detection, wide-band detection, narrow-spectrum detection and the like can be realized.

The invention discloses a metal gallium oxide doping transparent conductive membrane used for ultraviolet waveband and a preparation method thereof. The method comprises the steps that a layer of contact layer membrane firstly grows on a substrate, and annealing is conducted at the nitrogen-oxygen atmosphere of 400 DEG C-600 DEG C by a rapid thermal annealing furnace after the contact layer membrane grows; a first Ga2O3 membrane layer grows through sputtering under the condition of magnetic controlled argon sputtering; a doped membrane grows through sputtering under the condition of magnetic controlled argon sputtering; a second Ga2O3 membrane layer grows through sputtering under the condition of magnetic controlled argon sputtering, and annealing is conducted on completely growing membranes integrally at the nitrogen-oxygen atmosphere of 500 DEG C-600 DEG C by the rapid thermal annealing furnace, and membrane materials mutually penetrate, disperse and melt to form the metal doped Ga2O3 membrane. The transparent conductive membrane has higher membrane optical permeability and lower membrane square resistance on the basis of an ITO transparent conductive membrane.

The invention provides a method for realizing a waveguide-microstrip transition structure in the millimeter wave frequency band. The steps of the method include: 1. opening a narrow groove on the wide wall on one side of the waveguide; Metal thin film pattern sputtering is carried out on both sides, 50 ohm microstrip transmission line, microstrip impedance transformation line, positioning mark circuit and probe circuit are formed on the front side, and a metal layer with an extension part is formed on the back side, and the probe circuit is formed by traditional suspension The stripline is improved to a combined form of a microstrip line and a suspended stripline; 3. The back of the dielectric substrate is bonded in the narrow slot with conductive glue, and the probe circuit is vertically suspended in the waveguide. The waveguide-probe circuit transition structure obtained by this method is suitable for microwave products in the millimeter wave or even higher frequency bands. On the premise of ensuring the excellent performance of the transition structure, it greatly reduces the uncertainty caused by manual assembly and ensures Consistency of product assembly.

The invention relates to the field of power semiconductor devices, in particular to an injection reinforced bipolar transistor of an insulated gate. The injection reinforced bipolar transistor comprises a p-type collector electrode, wherein a carrier diffusion layer is arranged on the p-type collector electrode. A plurality of grooves are longitudinally arranged on the carrier diffusion layer. A plurality of rows of p-type active zones and a plurality of rows of p-type non-active zones are transversely arranged on the carrier diffusion layer and form a strip-shaped p-type base region. The injection reinforced bipolar transistor is provided with strip-shaped periodic separate cell structures, emitting electrodes are correspondingly in separate shapes, accordingly holes generate the accumulative effect in the zones not covered by the emitting electrodes, further the carrier concentration of the zones close to the grooves is improved, and the on-state voltage drop is reduced.

The invention provides a groove-type MOS (Metal-Oxide-Semiconductor) device and a manufacturing method thereof. The groove-type MOS device at least includes a first conductive heavily doped substrate,a first conductive lightly doped epitaxial layer on the first conductive heavily doped substrate, a plurality of first conductive source regions, a plurality of grooves, a gate oxide layer and a polysilicon gate which are formed in the each groove, a second conductive lightly doped body region formed on the upper portion of the first conductive lightly doped epitaxial layer, a cellular region contact hole formed in the second conductive lightly doped body region, an insulating dielectric block covering the polysilicon gate in the groove of the cellular region, a second conductive heavily doped body contact region formed between two adjacent first conductive source regions of the cellular region, and a metal source electrode formed in the contact hole of the cellular region, wherein the plurality of first conductive source regions and the plurality of grooves are formed on the upper portion of the first conductive lightly doped epitaxial layer at intervals. The groove-type MOS device can guarantee stability of the device while improving the device density and reducing the conduction resistance.

The invention discloses a PMOS (p-channel metal-oxide-semiconductor field-effect transistor) source / drain region ion implantation method and a corresponding device manufacturing method. Since an amorphous carbon layer can be completely removed without causing silicon sinking, when the amorphous carbon layer is used as a pad layer for PMOS source / drain region ion implantation, the range of implanted impurities in the silicon substrate can be reduced on the premise of basically not changing the implanted impurity distribution, thereby obtaining an ultrashallow junction which is more shallow than that obtained by a conventional method; or the implanted energy is increased on the premise of keeping the depth of the ultrashallow junction unchanged, thereby relieving the demands of technique for high-dose low-energy ion implantation to some extent, and lowering the technical difficulty of PMOS source / drain region ion implantation. The PMOS source / drain region ion implantation method and the corresponding device manufacturing method provided by the invention can be used for improving the ion implantation technique of the ultrashallow junction in the PMOS source / drain region, and lowering the technical difficulty.

The invention provides a high creep-resistant ultra-high molecular weight polyethylene fiber and a preparation method thereof. The preparation method is as follows: S1, mixing ultra-high molecular weight polyethylene powder, mixed solvent, antioxidant and sensitizer in a predetermined proportion, and stirring to obtain a uniform mixed suspension; S2, placing the mixed suspension in a twin-screw extruder After spinning out of the machine, the primary jelly filaments are obtained through a cooling water bath; the nascent jelly filaments are extracted with a mixed extract containing antioxidants and then dried, and then subjected to multi-stage thermal drawing and multi-stage heat drawing. graded oven to obtain the initial fiber product; S3, radiation crosslinking: the initial fiber product is subjected to a predetermined dose of irradiation treatment, and finally annealed under nitrogen conditions to obtain high creep-resistant ultra-high molecular weight polyethylene fibers. Compared with conventional ultra-high molecular weight polyethylene fibers, the fiber creep elongation of the high-creep-resistant ultra-high molecular weight polyethylene fibers prepared by the present invention is reduced by 50% or more.

The invention relates to a transistor and a transistor forming method, wherein the transistor forming method comprises the following steps that a semiconductor substrate is provided; at least two grooves are formed in the semiconductor substrate; insulation layers filling the grooves are formed in the grooves, and in addition, the tops of the insulation layers are set to be lower than the surface of the semiconductor substrate; epitaxial layers are formed on the surface and the side wall of the semiconductor substrate higher than the tops of the isolation layers, and in addition, the epitaxial layers are enabled to cover the partial isolation layers arranged at the two sides of the semiconductor substrate; a well region is formed in the semiconductor substrate and the epitaxial layers; a gate electrode structure is formed on the surface of each epitaxial layer, wherein each gate electrode structure comprises a gate dielectric layer covering the surface of the corresponding epitaxial layer and a gate conducting layer positioned on the top of the grate dielectric layer; light doping regions are formed in the epitaxial layers arranged at the two sides of the grate conducting layers; a heavy doping region is formed in each light doping region, and in addition, the heavy doping regions and the well region are isolated by the light doping regions and the isolation layers. The transistor formed by the method provided by the invention has low power consumption, the operation speed is high, the groove dimension is small, and in addition, the warping effect can be effectively eliminated.

The invention relates to a microbolometer with a high filling factor and a preparation method thereof. A metal reflective layer (2), an insulating medium layer (3) and a sacrificial layer ( 4), after the support layer (5), metal electrode layer (6), thermal sensitive layer (8), and passivation layer (9), combine chemical mechanical polishing, tungsten plunger or physical vapor deposition, chemical vapor deposition, electrochemical Deposition and other technologies prepare electrical connection structures with high aspect ratios, reduce the area of ​​electrical connection structures, and increase the fill factor of microbolometers. Infrared or terahertz detectors based on microbolometers are composed of array microbolometers with large arrays. By reducing the area of ​​contact holes, the fill factor can be effectively improved, and the performance of the detector can be improved at the same time. . Using this structure, it is possible to design and manufacture microbolometers with smaller pixels in the future to reduce the pixel size proportionally without increasing the difficulty of the process.

A thin film transistor and an array substrate. The thin film transistor comprises: a gate electrode (202); a gate electrode insulation layer (203) formed on the gate electrode and covering the gate electrode; an active layer (204) formed on the gate electrode insulation layer; a first material layer (205) formed on the active layer; and a source / drain electrode (206) formed on the first material layer. The first material layer comprises: a first ohmic contact layer (205a), a second ohmic contact layer (205c) and a high impedance interlayer (205b). The high impedance interlayer is formed between the first ohmic contact layer and the second ohmic contact layer, and an impedance thereof is greater than impedances of the first ohmic contact layer and the second ohmic contact layer. By means of the thin film transistor, a leakage current existing between a source / drain electrode and an active layer can be effectively reduced, and the manufacturing process therefor is simple.