229results about How to "Reduce RC delay" patented technology

An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.

The invention provides a TFT (Thin Film Transistor) array substrate. The arrangement mode of sub-pixels is changed to enable the uneven brightness of sub-pixels on the space to be arranged in a staggered mode in the same frame image display cycle and accordingly the display defects of vertical bright and dark lines are overcome. The integral resistance of data lines can be reduced, the resistance capacity delay is reduced, and accordingly the wrong charging display of the tail ends of scanning lines or the data lines is avoided.

A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

A four color liquid crystal display (LCD) including red, green, blue, and white sub-pixels are provided. The LCD also includes a plurality of gate lines for transmitting gate signals to the sub-pixels and a plurality of data lines for transmitting data signals to the sub-pixels. The white sub-pixel is smaller than the other sub-pixels, and each of the data lines passes between adjacent two sub-pixels and includes at least one curved portion. Furthermore, the lengths of the data lines are substantially uniform.

The invention provides a TFT array substrate. The sub pixel arraying manner is changed, the sub pixels, with uneven brightness, of the space are arrayed in a staggered manner in the same frame image display period, and the display defects of vertical bright and dark lines are optimized; the entire resistance of a data line can be reduced, resistance-capacitance delay can be reduced, and wrong charge of the tail end of a scanning line or data line is avoided.

Techniques for reading data from memory cells in memory arrays are provided. Local read bit lines are coupled to logic gates such as NAND gates. The input terminals of each logic gate are coupled to receive signals from two of the local read bit lines. The output of the logic gate changes state when a signal on one of the local read bit lines changes state. The signal from the logic gates are transmitted to global bit lines. Memory arrays can have multiple global bit lines to reduce delays caused by resistance and capacitance on the wire. Repeater circuits can propagate a signal from one global bit line to another global bit line.

A semiconductor structure includes a static random access memory (SRAM) cell comprising a first pull-up MOS device, a first pull-down MOS device and a first pass-gate MOS device, a first metallization layer, and an inter-layer dielectric (ILD) underlying the first metallization layer, wherein the ILD comprises an upper portion and a lower portion, a first first-layer contact in the lower portion of the ILD and connecting at least two of the first pull-up MOS device, the first pull-down MOS device and the first pass-gate MOS device. The first first-layer contact is physically isolated from second layer contacts in the upper portion of the ILD. The semiconductor structure further includes a second first-layer contact in the lower portion of the ILD, and a second-layer contact having at least a portion on the second first-layer contact, wherein the second layer contact electrically connects the second first-layer contact.

The present invention provides a thin-film transistor (TFT) array substrate. The TFT array substrate is structured to change the way that sub-pixels are arranged so that during a displaying period of a frame of image, the sub-pixels that have inconsistent brightness / darkness become alternate with each other spatially so that a displaying defect of vertical bright / dark lines can be improved and the overall resistance of the data line can be reduced to thereby reduce resistance-capacitance delay and prevent incorrect charging at a tail end of a scan line or a data line.

The invention belongs to the field of fabrication and interconnection of integrated circuits, and particularly relates to a mixed-media copper-diffusion-resistant blocking layer for copper interconnection and a manufacturing method of the blocking layer. The mixed-media copper-diffusion-resistant blocking layer has the advantages that the mixed media (oxidation layer / metal) is used as the copper-diffusion-resistant blocking layer, so that (1) the diffusion resistance of metal on copper can be effectively enhanced, the blocking layer is effectively prevented from being oxidized and falling, and the service life of the diffusion blocking layer is prolonged; (2) the effective dielectric constant value of interconnected circuits can be reduced, and further the whole RC delay of the interconnected circuits is reduced; and (3) since the metal and copper have good adhesion and contact, copper can be directly electroplated on the surface of the metal without depositing a layer of copper seed crystal firstly, so that the process is simple and feasible, and is expected to be applied to fabrication of the diffusion blocking layer of copper interconnection in future.