778results about How to "Improve etch selectivity" patented technology

A method for forming an insulation film having filling property on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and forming an insulation film constituted by Si, O, H, and optionally C or N on a substrate by plasma reaction using a combination of low-frequency RF power and high-frequency RF power in the reaction space. The plasma reaction is activated while controlling the flow of the reaction gas to lengthen a residence time, Rt, of the reaction gas in the reaction space.

A method of fabricating a driver circuit for use with a passive matrix or active matrix electrooptical display device such as a liquid crystal display. The driver circuit occupies less space than heretofore. A circuit (stick crystal) having a length substantially equal to the length of one side of the matrix of the display device is used as the driver circuit. The circuit is bonded to one substrate of the display device, and then the terminals of the circuit are connected with the terminals of the display device. Subsequently, the substrate of the driver circuit is removed. This makes the configuration of the circuit much simpler than the configuration of the circuit heretofore required by the TAB method or COG method, because conducting lines are not laid in a complex manner. The driver circuit can be formed on a large-area substrate such as a glass substrate. The display device can be formed on a lightweight material having a high shock resistance such as a plastic substrate. Hence, a display device having excellent portability can be obtained.

A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a variable DC power supply to apply a DC voltage to the upper electrode, so as to cause the absolute value of a self-bias voltage on the surface thereof to be large enough to obtain a suitable sputtering effect on the surface, and to increase the plasma sheath length on the upper electrode side to generate predetermined pressed plasma.

The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide transistor can have great potential in ferroelectric non volatile memory device with the further advantages of good interfacial properties with the ferroelectric materials, possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem to improve the reliability of the ferroelectric memory transistor. The semiconductive metal oxide film is preferably a metal oxide exhibiting semiconducting properties at the transistor operating conditions, for example, In2O3 or RuO2. The present invention ferroelectric transistor can be a metal-ferroelectric-semiconductive metal oxide FET having a gate stack of a top metal electrode disposed on a ferroelectric layer disposed on a semiconductive metal oxide channel on a substrate. Using additional layer of bottom electrode and gate dielectric, the present invention ferroelectric transistor can also be a metal-ferroelectric-metal (optional)-gate dielectric (optional)-semiconductive metal oxide FET.

Embodiments of the present technology may include a method of etching a substrate. The method may include striking a plasma discharge in a plasma region. The method may also include flowing a fluorine-containing precursor into the plasma region to form a plasma effluent. The plasma effluent may flow into a mixing region. The method may further include introducing a hydrogen-and-oxygen-containing compound into the mixing region without first passing the hydrogen-and-oxygen-containing compound into the plasma region. Additionally, the method may include reacting the hydrogen-and-oxygen-containing compound with the plasma effluent in the mixing region to form reaction products. The reaction products may flow through a plurality of openings in a partition to a substrate processing region. The method may also include etching the substrate with the reaction products in the substrate processing region.

Embodiments of the present technology may include a method of etching a substrate. The method may include striking a plasma discharge in a plasma region. The method may also include flowing a fluorine-containing precursor into the plasma region to form a plasma effluent. The plasma effluent may flow into a mixing region. The method may further include introducing a hydrogen-and-oxygen-containing compound into the mixing region without first passing the hydrogen-and-oxygen-containing compound into the plasma region. Additionally, the method may include reacting the hydrogen-and-oxygen-containing compound with the plasma effluent in the mixing region to form reaction products. The reaction products may flow through a plurality of openings in a partition to a substrate processing region. The method may also include etching the substrate with the reaction products in the substrate processing region.

A perpendicular magnetic recording (PMR) head is fabricated with a pole tip shielded laterally by a separated pair of side shields and shielded from above by an upper shield. The side shields are formed by a RIE process using specific gases applied to a shield layer through a masking layer formed of material that has a slower etch rate than the shield material. A masking layer of Ta, Ru / Ta, TaN or Ti, formed on a shield layer of NiFe and using RIE gases of CH3OH, CO or NH3 or their combinations, produces the desired result. The differential in etch rates maintains the opening dimension within the mask and allows the formation of a wedge-shaped trench within the shield layer that separates the layer into two shields. The pole tip is then plated within the trench and, being aligned by the trench, acquires the wedge-shaped cross-section of the trench. An upper shield is then formed above the side shields and pole.

A plasma reactor for processing a workpiece includes a vacuum enclosure, including a wall, defining a vacuum chamber, the vacuum chamber having a main chamber portion on one side of the wall and a plenum on another side of the wall, the plenum communicating with the chamber portion through at least one opening in the wall, a workpiece support within the main chamber portion and facing the wall. A gas distribution plate is adjacent the wall and faces the workpiece support and is coupled to a reactive process gas supply for injecting reactive process gases directly into a process region adjacent the workpiece support. A gas injection port at the plenum is coupled to a diluent gas supply for injecting diluent gases into the plenum. A coil antenna adapted to accept RF power is inductively coupled to the interior of said plenum, and is capable of maintaining a plasma in a reentrant path through the plenum and across the process region.

A method of processing a workpiece in a plasma reactor includes establishing a torroidal path for a plasma current to flow that passes near and transverse to the surface of said workpiece, maintaining a plasma current in the torroidal path by applying RF power to a portion of the torroidal path away from the surface of the workpiece, and increasing the ion density of the plasma current in the vicinity of the workpiece by constricting the area of a portion of the torroidal path overlying the workpiece.

The invention is embodied in a method of processing a semiconductor workpiece in a plasma reactor chamber, including supplying a polymer and etchant precursor gas containing at least carbon and fluorine into the chamber at a first flow rate sufficient of itself to maintain a gas pressure in the chamber in a low pressure range below about 20 mT, supplying a relatively non-reactive gas into the chamber at second flow rate sufficient about one half or more of the total gas flow rate into the chamber, in combination with the first flow rate of the precursor gas, to maintain the gas pressure in the chamber in a high pressure range above 20 mT, and applying plasma source power into the chamber to form a high ion density plasma having an ion density in excess of 1010 ions per cubic centimeter. In one application of the invention, the workpiece includes an oxygen-containing overlayer to be etched by the process and a non-oxygen-containing underlayer to be protected from etching, the precursor gas dissociating in the plasma into fluorine-containing etchant species which etch the oxygen-containing layer and carbon-containing polymer species which accumulate on the non-oxygen-containing underlayer. Alternatively, the high pressure range may be defined as a pressure at which the skin depth of the inductive field exceeds {fraction (1 / 10)} of the gap between the inductive antenna and the workpiece.

A composite hard mask is disclosed that prevents build up of metal etch residue in a MRAM device during etch processes that define an MTJ shape. As a result, MTJ shape integrity is substantially improved. The hard mask has a lower non-magnetic spacer, a middle conductive layer, and an upper sacrificial dielectric layer. The non-magnetic spacer serves as an etch stop during a pattern transfer with fluorocarbon plasma through the conductive layer. A photoresist pattern is transferred through the dielectric layer with a first fluorocarbon etch. Then the photoresist is removed and a second fluorocarbon etch transfers the pattern through the conductive layer. The dielectric layer protects the top surface of the conductive layer during the second fluorocarbon etch and during a substantial portion of a third RIE step with a gas comprised of C, H, and O that transfers the pattern through the underlying MTJ layers.

A composite hard mask is disclosed that enables sub-100 nm sized MTJ cells to be formed for advanced devices such as spin torque MRAMs. The hard mask has a lower non-magnetic metallic layer such as Ru to magnetically isolate an overlying middle metallic spacer such as MnPt from an underlying free layer. The middle metallic spacer provides a height margin during subsequent processing to avoid shorting between a bit line and the MTJ cell in the final device. An upper conductive layer may be made of Ta and is thin enough to allow a MTJ pattern in a thin overlying photoresist layer to be transferred through the Ta during a fluorocarbon etch without consuming all of the photoresist. The MTJ pattern is transferred through the remaining hard mask layers and underlying MTJ stack of layers with a second etch step using a C, H, and O etch gas composition.

The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide transistor can have great potential in ferroelectric non volatile memory device with the further advantages of good interfacial properties with the ferroelectric materials, possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem to improve the reliability of the ferroelectric memory transistor. The semiconductive metal oxide film is preferably a metal oxide exhibiting semiconducting properties at the transistor operating conditions, for example, In2O3 or RuO2. The present invention ferroelectric transistor can be a metal-ferroelectric-semiconductive metal oxide FET having a gate stack of a top metal electrode disposed on a ferroelectric layer disposed on a semiconductive metal oxide channel on a substrate. Using additional layer of bottom electrode and gate dielectric, the present invention ferroelectric transistor can also be a metal-ferroelectric-metal (optional)-gate dielectric (optional)-semiconductive metal oxide FET.

The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC).A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.