58results about How to "Affect electrical properties" patented technology

Provided are a polymer solar cell and a preparation method thereof. The cell comprises a transparent positive pole, hole transporting layers, an optical active layer and a metal negative pole, wherein the hole transporting layers comprise a first hold transporting layer and a second hold transporting layer, the first hole transporting layer is arranged on the surface of the transparent positive pole, and metal nano materials are doped in the first hole transporting layer; the second hold transporting layer is arranged on the surface of the first hole transporting layer; and metal nano materials are doped in the optical active layer. According to the polymer solar cell and the preparation method, the exposed metal nano materials in the first hole transporting layer are coated, the exposed metal nano materials in the first hole transporting layer and the optical active layer in the cell form good ohmic contact, the electrical property of the cell are prevented from being influenced due to leading-in of the metal nano materials, the fact that open-circuit voltage and filling factors of the cell are not reduced is guaranteed, and meanwhile photoelectric conversion efficiency is improved by more than 10%.

The invention discloses a preparation method for anti-dielectric substrate delamination of a multi-layer FSS radome. Before the radome is laminated, the polyimide frequency selective surface is plasma activated and the cyanate resin is sprayed for viscosity-increasing treatment; Quantitatively describe the influence of curing process parameters on the internal stress, establish the relationship model between the internal stress of the multilayer frequency selective surface stealth radome and the curing process parameters, and then make the polyimide frequency selective surface into prepreg; select according to the multilayer frequency The circuit design of the surface stealth radome requires the frequency selective surface and the layup sequence design of the composite material dielectric layer, and the layup is carried out according to the layup sequence; after the layup is completed, the autoclave is formed and cured. The invention makes up for the defect that air bubbles are easily trapped when the polyimide frequency selective surface and the dielectric layer prepreg are laminated in the traditional method, and solves the problem that the air bubbles cannot be excluded due to the barrier of the frequency selective surface when the dielectric layer is formed, and separation will occur. layer problem.

A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer (56) that is thick enough to fully convert the semiconductor layer (22) to a semiconductor metal alloy in a first MOSFET type region (40) but only thick enough to partially convert the semiconductor layer (20) to a semiconductor metal alloy in a second MOSFET type region (30). In one embodiment, the gate stack in a first MOSFET region (40) is recessed prior to forming the metal-containing layer (56) so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer (56) is thinned over a first type MOSFET region (40) relative to a second type MOSFET region (30) prior to the conversion process.

The invention discloses a step-by-step printing device for photovoltaic crystalline silicon cells, which includes a material ladder, a placement plate, a first installation frame, a load-bearing plate, a clamping frame, a screw rod, a liquid barrel, an infusion tube, a clamping mold frame, and an infrared sensor , the first printing board, the second printing board, the third printing board, the card mold device and the limit printing device, the bottom of the material ladder is welded and fixed with the installation column, the top of the placement board is provided with a placement slot, and the first The installation frame is fixed on both sides of the top of the material ladder, wire blocks are fixed on both sides of the load-bearing plate, first clamping holes are opened on both sides of the clamping frame, and the step-by-step printing device of the photovoltaic crystal silicon cell is equipped with a first printing board, the second printing board, and the third printing board, it is convenient to print the main grid line, sub-grid line and auxiliary grid line through different printing boards, so as to avoid the duplication of position during the printing process of the main grid line due to the transformation of the overall crystalline silicon cell printing Printing, thereby reducing the electrical performance of the overall crystalline silicon cell.

The invention discloses a display substrate, a preparation method thereof, and a display panel. The display substrate comprises: a base substrate; a first insulating layer and a second insulating layer are arranged on the base substrate, wherein the first insulating The film stress direction of the layer is the same as the film stress direction of the second insulating layer. The display substrate is beneficial to improve the display uniformity of the image, avoid display defects such as white spots, and improve the display effect of the display image.

The invention discloses an interlayer film manufacturing method. The interlayer film manufacturing method comprises the following steps: step one, providing a semiconductor substrate on which a pattern structure of a semiconductor device is formed; step two, forming a first insulating layer on the bottom surface and side surfaces of the pattern spacer and the surface of the pattern structure outside the pattern spacer; step three, forming a second insulating layer to completely fill the pattern spacer and extend outside the pattern spacer; and step four: performing chemical mechanical polishing on the second insulating layer and the first insulating layer with the pattern structure as a stop layer, and forming the interlayer film formed by stacking the first and second insulating layers filled in the pattern spacer. The interlayer film manufacturing method can reduce or eliminate dishing defects on the interlayer film surface at the top of the pattern spacer, can improve the flatness of the entire interlayer film, and can improve the electrical properties of semiconductor devices.