Manufacturing method of interlayer film

Abstract

The invention discloses an interlayer film manufacturing method. The interlayer film manufacturing method comprises the following steps: step one, providing a semiconductor substrate on which a pattern structure of a semiconductor device is formed; step two, forming a first insulating layer on the bottom surface and side surfaces of the pattern spacer and the surface of the pattern structure outside the pattern spacer; step three, forming a second insulating layer to completely fill the pattern spacer and extend outside the pattern spacer; and step four: performing chemical mechanical polishing on the second insulating layer and the first insulating layer with the pattern structure as a stop layer, and forming the interlayer film formed by stacking the first and second insulating layers filled in the pattern spacer. The interlayer film manufacturing method can reduce or eliminate dishing defects on the interlayer film surface at the top of the pattern spacer, can improve the flatness of the entire interlayer film, and can improve the electrical properties of semiconductor devices.

Description

Technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing an interlayer film. Background technique [0002] Such as Figure 1A to Figure 1E What is shown is a device structure diagram in each step of the existing manufacturing method of the interlayer film. The existing manufacturing method of the interlayer film 107 includes the following steps: [0003] Step one, such as Figure 1A As shown, a semiconductor substrate 101 is provided, and a pattern structure of a semiconductor device is formed on the semiconductor substrate 101, and the area between each pattern structure is a pattern spacer. [0004] Generally, the semiconductor substrate 101 is a silicon substrate. [0005] The semiconductor device is a MOS transistor with HKMG. HKMG has a high dielectric constant (HK) gate dielectric layer and a metal gate (MG), so it is usually abbreviated as HKMG in the art. [0006] The interlayer fi...

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Problems solved by technology

[0019] However, by Figure 1D It can be seen that, due to the existence of the butterfly defect formed by the concave surface of the interlayer film 107, metal remains at the butterfly defect, and the residual metal is as marked 109a

[0020] Residual metal 109a obviously affects the performance of the device

In order to eliminate the influence of the residual metal 109a, the only way is to perform CMP to thin the interlayer film 107 and the metal gate 109, but the embedded silicon germanium layer 108 is prone to be exposed. risk, the exposure of the embedded silicon germanium layer 108 will adversely affect the electrical performance of the semiconductor device

At the same time, in order to eliminate the increased CMP of the residual metal 109a, the increase of the cost is also brought

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