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670results about How to "Reduce electric field strength" patented technology

Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a "keyhole" shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.
Owner:ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED

Active matrix display device

In an active matrix display device, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shaped semiconductor region, is used as a switching element. Each of the TFT have offset regions and lightly doped drain (LDD) regions. Then, by supplying a selection signal to the gate lines, the TFTs are operated, thereby writing data to the pixel, while a suitable voltage is supplied to the capacitance line, a channel is formed thereunder and it becomes a capacitor. Thus the amount of discharge from the pixel electrode is reduced by the capacitor.
Owner:SEMICON ENERGY LAB CO LTD

Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.
Owner:ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED

Method and device for integrally desulfurizing, denitrating and dust-removing by plasma

The invention discloses an integrated treatment method capable of desulfurizing, denitrating and dust-removing at the same time, and provides a device which adopts the treatment method. Smoke formed after the combustion in a boiler contains the main ingredients of SO2, NOX and dust, and passes through a plasma generation electrode; generated plasmas contain a large amount of high-energy electronics and act on O2 and H2O to generate a large quantity of active particles, such as H, O, OH and O3. The SO2 and the NOX can perform chemical reaction to generate high-valence state sulfur oxides and nitrogen oxides under the effect of the active particles, and then the sulfur oxides and the nitrogen oxides are combined with introduced ammonia gas to generate ammonium salts; the ammonium salts are recovered and serve as secondary products; and therefore, the desulfurizing and the denitrating are realized. In the process, charged particles in the plasmas can electrify dust particles, so that the charged particles can move directionally under the effect of an additional direct-current bias electric field; and therefore, the function of removing the dust is realized. According to the method and the device, the static electricity dust removal and the plasma desulfurizing and denitrating are integrated, so that the number of power supplies is reduced, the efficiency of a discharge power supply is improved, the energy consumption can be reduced, the investment is saved, the occupied area is reduced, and the cost is reduced.
Owner:BEIJING RUIYUDA TECH

N type SOI lateral double-diffused metal-oxide semiconductor transistor

A laterally double diffused metal oxide semiconductor transistor of an N-shaped silicon-on-insulator (SOI) comprises a semiconductor substrate. A buried oxide is arranged on the semiconductor substrate, an N-shaped doped semiconductor drift region is arranged on the buried oxide and a P-shaped well region is arranged above the N-shaped doped semiconductor drift region, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the transistor. An N-shaped source region and a P-shaped contact region are arranged in a P-shaped well. The transistor is characterized in that the transistor also comprises at least a layer of floating oxide structure which is positioned in the N-shaped doped semiconductor drift region between a drain region and the buried oxide; moreover, a plurality of layers of floating oxide structure are allowed to further optimize the distribution of longitudinal electric fields in the drain region, thereby increasing the entire breakdown voltage of the transistor.
Owner:SOUTHEAST UNIV

Image displaying device

An image displaying device having multiple photosensing devices have successfully suppressed a leakage current from each photosensing device and improved the S / N ratio. In the image displaying device, pixels and photosensing devices are disposed as pairs in a matrix pattern on a substrate. Each of the pixels and each of the photosensing devices are driven independently. Each photosensing device includes a semiconductor layer that is a photoelectric conversion layer connected to at least a first electrode and a second electrode. The contact surfaces of the first and second electrodes with respect to the semiconductor layer are disposed so that their center axes are separated from each other.
Owner:PANASONIC LIQUID CRYSTAL DISPLAY CO LTD +1

Method for fabricating a mask ROM

The present invention discloses a method for fabricating a buried bit line of a mask ROM. The method includes providing a semiconductor substrate with a photoresist layer, and patterning the photoresist layer to form a photoresist pattern. A first ion implantation process is performed to form a first doped region in the semiconductor substrate not covered by the photoresist pattern. Then, an organic layer is coated on the photoresist pattern and the semiconductor substrate and an etching process is performed to form an organic spacer at two sides of the photoresist pattern. Finally, a second ion implantation process forms a second doped region in the semiconductor substrate not covered by the photoresist pattern and the organic spacer. Finally, the photoresist pattern and the organic spacer are removed.
Owner:UNITED MICROELECTRONICS CORP
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