110results about How to "Reduce reverse leakage" patented technology

The invention discloses a Schottky diode and a manufacturing method thereof. The Schottky diode comprises a substrate, a first semiconductor layer, a second semiconductor layer, a first passivation dielectric layer, a cathode, an anode slot, a low work function anode and a high work function anode, wherein the first semiconductor layer is located on the substrate; the second semiconductor layer is located on the first semiconductor layer, and a two-dimensional electron gas is formed at the at the interface between the first semiconductor layer and the second semiconductor layer; the first passivation dielectric layer is located on the second semiconductor layer, and a part of the second semiconductor layer is exposed out of the first passivation dielectric layer; the cathode is arranged on the exposed part of the second semiconductor layer or extends to the upper surface of the first passivation dielectric layer; the anode slot extends from the first passivation dielectric layer to a region where the two-dimensional electron gas is positioned or exceeds the region where the two-dimensional electron gas is positioned; the low work function anode is arranged on the anode slot and extends to the upper surface of the second semiconductor layer; and the high work function anode covers the low work function anode, and is electrically connected with the low work function anode. The Schottky diode provided by the invention has the advantages of being low in reverse electric leakage, high in breakdown voltage, low in forward threshold voltage and turn-on resistance.

The invention discloses a SiC vertical double diffused metal-oxide-semiconductor (VDMOS) device and a fabrication method thereof, and belongs to the technical field of a power semiconductor. A poly-silicon layer is directly deposited on a surface of a junction field-effect transistor (JFET) region of the SiC VDMOS device to form a Si / SiC heterojunction, a diode is further integrated in the device, and the application of the device in the field of an inversion circuit, a chopping circuit and the like is optimized. Compared with the prior art directly employing a VDMOS parasitic SiC diode, the SiC VDMOS device has the advantages of relatively low power loss, relatively fast working speed and relatively high working efficiency, and positive conduction is easier to achieve; compared with the prior art that a fast recovery diode (FRD) is reversely connected with the exterior of the device in parallel, the SiC VDMOS device has the advantages that the usage number of the device is reduced, connection lines between the devices are reduced, and the miniature development of the device is promoted; moreover, the grid width is reduced, the grid capacitance is reduced, and the working speed of the device is further increased; and therefore, the VDMOS device proposed by the invention has wide application prospect in the circuit field of the inversion circuit, the chopping circuit and the like.

A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.

The present invention discloses a manufacturing method of trench Schottky. The method comprises the following steps of: a. performing epitaxy of a buffer layer on an N+ heavily-doped substrate; and b.growing n lightly-doped layers in order on the buffer layer. The buffer layer with relatively high dosage concentration is subjected to epitaxy and is configured to further reduce the forward conduction voltage drop of a device and reduce the resistance of a drifting region on the premise of ensuring the withstand voltage of the device, one or more than one lightly-doped layers with gradually reduced dosage concentration are subjected to epitaxy to gradually increase the electrical resistivity of each layer to effectively reduce the backward electric leakage of the device, achieve the withstand voltage optimization of a barrier region and a trench, achieve the regulation of the epitaxial electrical resistivity, effectively reduce the electric leakage and conduction voltage drop of the trench Schottky products and further improve the device performances; the substrate materials employ a multi-layer epitaxy mode to improve the performances of the device with no need for extra increasingof special processes, and compared to the complete compatibility in the prior art, the processing cost is reduced.

The present invention provides a preparation method of a trench type Schottky diode. The method includes the following steps that: photoetching and etching are performed on a semiconductor silicon substrate of which the surface is sequentially provided with a silicon oxide layer and a silicon nitride layer, so that etching windows can be formed; by means of the etching windows, the N type epitaxial layer of the semiconductor silicon substrate is etched, so that silicon trenches can be formed; the silicon nitride layer is removed, so that a gate oxide layer can be formed on the surface of the entire device; a first polycrystalline silicon layer is deposited on the surface of the entire device, the first polycrystalline silicon layer is etched, so that a second polycrystalline layer is formed in the silicon trenches; and a dielectric layer and a metal layer are sequentially formed on the surface of the entire device. The N type epitaxial layer among adjacent silicon trenches can well contact with the metal layer, so that the contact performance of a Schottky barrier formed between the N type epitaxial layer among the adjacent silicon trenches and the metal layer can be excellent; and since the Schottky barrier is good, the reverse current leakage of the trench type Schottky diode can be decreased, and the performance of the trench type Schottky diode can be improved.

The present invention provides a bidirectional interlayer isolation well with low power consumption and high reliability. The bidirectional interlayer isolation well comprises a substrate and a longitudinal isolation well region and a first buried layer arranged on the substrate, the first buried layer is arranged around the longitudinal isolation well region, the longitudinal isolation well region is provided with a first well region and a transverse isolation well region, the transverse isolation well region is arranged around a first well region, a second well region is arranged on the first buried layer and arranged around the transverse isolation well region, the first well region, the transverse isolation well region and the second well region commonly form two transverse PNP structures, the first well region, the longitudinal isolation well region and the substrate commonly form two longitudinal PNP structures, when the first well region encounters a high voltage, the two transverse PNPs and the two longitudinal PNPs cannot be subjected to amplification and bias due to the same-potential arrangement of the transverse isolation well region so as to effectively weaken the leakage currents in horizontal and vertical directions. The bidirectional interlayer isolation well with low power consumption and high reliability is scientific in design, high in isolation, low in reverse leakage and high in reliability.

A semiconductor device and a preparation method are provided. Due to the fact that the composite anode structure of the first anode Ohmic junction and the second anode MIS junction is adopted to replace a traditional Schottky junction anode, and the rectification characteristic of a traditional Schottky junction is replaced by the channel regulation characteristic of the MIS junction, the two parameter indexes of the reverse leakage current (IR) and the forward opening voltage (VoN) of the semiconductor device are simultaneously improved. Meanwhile, in the preparation method disclosed by the invention, the technical scheme and conditions used in the whole manufacturing process can be realized through the standard Fab technology, the process is simple, and the number of times of windowing when optimizing the design of traditional semiconductor device terminals is reduced.