The invention discloses a self-aligned silicon carbide metal-oxide-semiconductor field-effect-transistor (MOSFET) device with an optimized P<+> region and a fabrication method of the self-aligned silicon carbide MOSFET device. The self-aligned silicon carbide MOSFET device is formed by connecting a plurality of same cells in parallel, and the cells of the silicon carbide MOSFET device are uniformly arranged. Each cell of the silicon carbide MOSFET device comprises two sources, a grid, a grid oxide layer, two N<+> source regions, two P<+> contact regions, two P pits, an N<-> drift layer, a buffer layer, an N<+> substrate, a drain and an isolation dielectric layer. By optimizing the P<+> region, favorable source ohmic contact is formed, the on resistance is reduced, meanwhile, the source and the P pits are in short connection, parasitic negative-positive-negative (PNP) and a parasitic transistor effect of PiN are prevented, the conduction property and the breakdown property of the device can be compatible, and the device can be used in a high-voltage and high-frequency silicon carbide MOSFET device. A self-aligned fabrication method is adopted by the invention, the process is simplified, the channel size is accurately controlled, and a transverse or longitudinal power MOSFET can be fabricated.