153 results about "Rms roughness" patented technology

Methods and articles are disclosed in which a substrate is provided with a photo-induced hydrophilic surface by forming a photo-induced hydrophilic coating on the substrate by spray pyrolysis, chemical vapor deposition, or magnetron sputter vacuum deposition. The coating can have a thickness of 50 Å to 500 Å, a root mean square roughness of less than 5, preferably less than 2, and photocatalytic activity of less than 3.0×10−3 cm−1 min−1±2.0×10−3 cm−1 min−1. The substrate includes glass substrates, including glass sheets and continuous float glass ribbons.

A substrate with a textured surface is disclosed. The substrate may be, for example, a light emitter comprising a light guide, for example a backlight element for use in a display device, wherein a surface of the light guide, for example a glass substrate, is configured to have a textured surface with a predetermined RMS roughness and a predetermined correlation length of the texture. A plurality of light scatter supressing features can be provided on the textured surface. Textured surfaces disclosed herein may be effective to reduce electrostatic charging of the substrate surface. Methods of producing the textured surface are also disclosed.

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

A III–V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III–V nitride-based microelectronic and opto-electronic devices.

Methods and articles are disclosed in which a substrate is provided with a photo-induced hydrophilic surface by forming a photo-induced hydrophilic coating on the substrate by spray pyrolysis, chemical vapor deposition, or magnetron sputter vacuum deposition. The coating can have a thickness of 50 Å to 500 Å, a root mean square roughness of less than 5, preferably less than 2, and photocatalytic activity of less than 3.0×10−3 cm−1 min−1±2.0×10−3 cm−1 min−1. The substrate includes glass substrates, including glass sheets and continuous float glass ribbons.

A glass substrate for a magnetic recording medium is formed to have a disc shape and includes ridge shaped textures 13 extending along concentric circles on a main surface. When measuring a 10 μm square range with an atomic force microscope, the textures have a width W that is between 10 and 200 nm. The textures have a height H that is between 2 and 10 nm. Further, the textures have a ratio (Rp / RMs) of a maximum mountain height with respect to a root mean square roughness that is less than or equal to 15. The textures include high frequency components superimposed on the low frequency components. It is preferable that the textures of the high frequency components have a width W′ that is between 0.1 and 20 nm, and the textures of the high frequency components have a height H′ that is between 0.1 and 1 nm.

A high-performance semiconductor device using an SOI substrate in which a low-heat-resistance substrate is used as a base substrate. Further, a high-performance semiconductor device formed without using chemical polishing. Further, an electronic device using the semiconductor device. An insulating layer over an insulating substrate, a bonding layer over the insulating layer, and a single-crystal semiconductor layer over the bonding layer are included, and the arithmetic-mean roughness of roughness in an upper surface of the single-crystal semiconductor layer is greater than or equal to 1 nm and less than or equal to 7 nm. Alternatively, the root-mean-square roughness of the roughness may be greater than or equal to 1 nm and less than or equal to 10 nm. Alternatively, a maximum difference in height of the roughness may be greater than or equal to 5 nm and less than or equal to 250 nm.

Methods for roll-to-roll deposition of optically transparent and high conductivity metallic thin films are disclosed. In general, a method according to the present invention comprises: (1) providing a flexible plastic substrate; (2) depositing a multi-layered conductive metallic film on the flexible plastic substrate by a thin-film deposition technique to form a composite film; and (3) collecting the composite film in continuous rolls. Typically, the thin conductive metallic film is an InCeO-Ag-InCeO film. Typically, the thin-film deposition technique is DC magnetron sputtering. Another aspect of the invention is a composite film produced by a method according to the present invention. Still another aspect of the invention is a composite film comprising InCeO-Ag-InCeO film formed on a flexible plastic substrate, wherein the composite film has a combination of properties including: transmittance of at least 90% throughout the visible region; an electrical resistance of no greater than about 10 Omega / square; a root-mean-square roughness of no greater than about 2.5 nm; and an interlayer adhesion between the InCeO / Ag / InCeO metallic film and the remainder of the composite film that is sufficiently great to survive a 180° peel adhesion test.

A nitrile-rubber medical exam glove composed of a glove body which is a flexible layer of nitrile-butadiene rubber. The glove body has a chlorinated first surface forming a donning side of the glove body and an un-chlorinated second surface forming a grip side of the glove body. The elastomeric glove also includes a substantially uniform distribution of a release agent distributed over the un-chlorinated second surface of the glove body. The elastomeric glove has: (a) an average thickness of between about 0.03 to 0.12 mm in a palm region of the glove body as measured in accordance with ASTM D3767, procedure A; (b) an un-chlorinated second surface of the glove body characterized by a Surface Root Mean Square Roughness of from about 3.00 μ m to about 6.55 μ m; and (c) a failure rate of less than about 1 percent when the elastomeric glove is subjected to pinhole leak testing generally in accordance with ASTM D5151-06.

A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns.

Methods for roll-to-roll deposition of optically transparent and high conductivity metallic thin films are disclosed. In general, a method according to the present invention comprises: (1) providing a flexible plastic substrate; (2) depositing a multi-layered conductive metallic film on the flexible plastic substrate by a thin-film deposition technique to form a composite film; and (3) collecting the composite film in continuous rolls. Typically, the thin conductive metallic film is an InCeO-Ag-InCeO film. Typically, the thin-film deposition technique is DC magnetron sputtering. Another aspect of the invention is a composite film produced by a method according to the present invention. Still another aspect of the invention is a composite film comprising InCeO-Ag-InCeO film formed on a flexible plastic substrate, wherein the composite film has a combination of properties including: transmittance of at least 90% throughout the visible region; an electrical resistance of no greater than about 10 Omega / square; a root-mean-square roughness of no greater than about 2.5 nm; and an interlayer adhesion between the InCeO / Ag / InCeO metallic film and the remainder of the composite film that is sufficiently great to survive a 180° peel adhesion test.

The invention provides a polishing technology of a zinc oxide single crystal substrate, which can meet the requirements for the epitaxial growth of a photoelectric device. The zinc oxide single crystal substrate with the surface RMS (root mean square) roughness of less than 1nm within a surface range of 10 mu m*10 mu m can be obtained through the steps of rough grinding of a single crystal, bonding, loading on a disc, mechanical rough grinding, mechanical fine grinding, mechanical rough polishing, chemical mechanical fine polishing, cleaning and packaging. The polishing technology relates to a bonding agent, a bonding technology and a technology of unloading from the disc used in the bonding process of the zinc oxide single crystal substrate, as well as grinding fluid, polishing fluid and a grinding thickness control technology used in the grinding process and the polishing process. The obtained zinc oxide single crystal substrate can be used for the epitaxial growth of a semiconductor photoelectric device.

The substrate-supported anode for a high-temperature fuel cell comprises an at least three-layer anode laminate on a metallic substrate. Each of the layers of the anode laminate comprises yttria-stabilized zirconia and nickel, wherein the mean particle size of the nickel decreases from one layer to the next as the distance from the substrate increases. The last layer of the anode laminate, which is provided for contact with the electrolyte, has a root mean square roughness of less than 4 μm. The overall mean pore size of this layer is typically between 0.3 and 1.5 μm. Starting powders having a bimodal particle size distribution of yttria-stabilized zirconia and nickel-containing powder are used at least for the first and second layers of the anode laminate. The mean particle size of the nickel-containing powder is reduced from one layer to the next, whereby it is advantageously no more than 0.5 μm in the last layer of the anode laminate.

Provided are an integrated conductive substrate simultaneously serving as a substrate and an electrode, and an electronic device using the same. The integrated conductive substrate includes a metal layer composed of a non-ferrous metal, which has a first surface having a first root mean square roughness, and a semiconductor layer containing a semiconductor material, which has a second surface having a second root mean square roughness and is formed on the first surface. Here, the semiconductor layer includes a semiconductor-type planarization layer formed by a solution process using at least one of the semiconductor material and a precursor of the semiconductor material to planarize the first surface of the metal layer, and the second root mean square roughness is smaller than the first root mean square roughness.

In a transparent conductive film for use in a transparent touch panel in which a lower electrode and an upper electrode are stacked so as to be spaced from each other by spacers, the transparent conductive film being provided on an electrode substrate of at least one of the electrodes and thereby forming the electrode, the transparent conductive film has, in its surface shape, an arithmetic mean roughness (Ra) within a range of 0.4 nm≦Ra≦4.0 nm and a root-mean-square roughness (Rms) within a range of 0.6 nm≦Rms≦3.0 nm.

The invention relates to a precise polishing method of a stainless steel substrate, comprising the following steps: preparing polishing solution in proportion; fixing the steel substrate 5 to be polished stainless at the bottom of a polishing head 4, allowing the polishing head 4 to act on a polishing block 6 by a pressure device 7, driving the polishing block 6 and the polishing head 4 to rotatewith the help of a rotating device, and transporting solution 2 to the surface of a polishing pad 1 to ensure the polishing solution 2, the polishing pad 1 and the stainless steel substrate 5 can contact with each other fully; carrying out chemical mechanical polishing on the surface of stainless steel substrate 5 till the surface becomes a complete mirror face; and then cleaning the surface of the stainless steel substrate 5 at once. The surface of the stainless steel substrate polished by the method provided in the invention is neat and smooth and the roughness concentration of root mean square is only 0.7 nano, thereby overcoming the problem that other polishing methods are unable to meet the requirements of flatness and roughness concentration.

Substrates suitable for mirrors which are used at wavelengths in the EUV wavelength range have a main body (2) and a polishing layer (3). The polishing layer (3) has a thickness of less than 10 μm and a root-mean-square roughness of less than 0.5 nm and the main body (2) is produced from an aluminum alloy. Moreover, a highly reflective layer (6) is provided on the polishing layer (3) of the substrate (1) of the EUV mirror (5).

A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns.

A novel electrically conductive polymer composite composed of polycaprolactone fumarate-polypyrrole (PCLF-PPy) for applications in nerve regeneration is disclosed. The synthesis and characterization of PCLF-PPy and in vitro studies showing PCLF-PPy supports both PC12 cell and Dorsal Root Ganglia neurite extension. PCLF-PPy composite materials were synthesized by polymerizing pyrrole in pre-formed scaffolds of PCLF resulting in an interpenetrating network of PCLF-PPy. PCLF-PPy composite materials possess electrical conductivity up to 6 mS cm−1 with compositions ranging from 5-13.5 percent polypyrrole of the bulk material. Surface topographies of PCLF-PPy materials show microstructures with a RMS roughness of 1195 nm and nanostructures with RMS roughness of 8 nm. PCLF-PPy derivatives were synthesized with anionic dopants to determine effects on electrical conductivity and to optimize the chemical composition for biocompatibility. In vitro studies using PC12 show PCLF-PPy composite materials induce a higher cellular viability and increased neurite extension compared to PCLF. PCLF-PPy composites doped with either naphthalene sulfonic acid or dodecyl benzene sulfonic acid are determined to be the optimal materials for electrical stimulation. In vitro studies showed significant increases in percentage of neurite bearing cells, number of neurites per cell and neurite length in the presence of ES compared to no ES. Additionally, extending neurites were observed to align in the direction of the applied current. Electrically conductive PCLF-PPy scaffolds possess material properties necessary for application as nerve conduits. Additionally, the capability to significantly enhance and direct neurite extension by passing electrical current through PCLF-PPy scaffolds renders them even more promising as future therapeutic treatments for severe nerve injuries.

In a magnetic recording medium, surface roughness of a glass substrate and the variation of the surface roughness are suppressed to the predetermined range. Namely, the surface roughness (Rmax, Ra, Rq) and the relation (Rmax / Ra) between Rmax and Ra are restricted to the predetermined range. In this event, Ra is representative of a center-line mean roughness, Rmax is defined as a maximum height representative of a difference between a highest point and a lowest point and Rq is representative of a root mean square roughness. Thereby, crystal grains of an underlying layer and a magnetic layer formed thereon are equalized. Specifically, the surface roughness is specified by Rmax≦15 nm, Ra≦1 nm and Rq≦1.5 nm. Further, the ratio between the surface roughness Rmax and the surface roughness Ra is specified by Rmax / Ra≦30.

The invention belongs to the technical field of electric materials and devices, and relates to a method for preparing a flexible polyester nickel-coating electrode. The method particularly comprises the following steps of: performing surface silicification modification on a polyester substrate, and introducing silane coupler molecules, of which the tail ends contain active groups such as sulfhydryl groups, amino groups and acylamino groups on the premise of not damaging surface flatness; performing catalytic activation on the polyester substrate in mixed solution of silver nitrate and glucose so as to make a thin layer of silver catalyst coated on the polyester substrate undergoing silicification, wherein the silver catalyst layer and the substrate are connected by chemical bonds; and finally performing chemical nickel-plating in the presence of silver catalyst. The polyester nickel-coating electrode prepared by the method has the advantages of strong adhesion between the nickel coating layer and the substrate, stripping strength of more than 40N / cm, high smoothness, root-mean-square roughness(Rrms) of less than 15nm (the area is 5mu m*5mu m), high electric conductivity, and lower resistivity (5.3 mu omega.cm) compared with that of pure nickel. The flexible polyester nickel-coating electrode can be widely applied to solar batteries, membrane ion secondary batteries, flexible organic electric devices, and the like.

A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.

There is provided a method of producing a photovoltaic device comprising a photoactive region comprising a layer of perovskite material, wherein the layer of perovskite material is disposed on a surface that has a roughness average (Ra) or root mean square roughness (R rms) of greater than or equal to 50 nm. The method comprises using vapour deposition to deposit a substantially continuous and conformal solid layer comprising one or more initial precursor compounds of the perovskite material, and subsequently treating the solid layer with one or more further precursor compounds to form a substantially continuous and conformal solid layer of the perovskite material on the rough surface. There is also provided a photovoltaic device comprising a photoactive region comprising a layer of perovskite material disposed using the method.

The invention provides a liquid crystal display panel and a liquid crystal alignment method thereof. The liquid crystal display panel comprises a first substrate unit, a second substrate unit and a display dielectric layer. The first substrate unit includes a first substrate and a first conducting layer, wherein the surface of the first conducting layer has a first surface root-mean-square roughness. The second substrate unit includes a second substrate and a second conducting layer, wherein the surface of the second conducting layer has a second surface root-mean-square roughness. The display dielectric layer is located between the first and second substrates and comprises a plurality of liquid crystal molecules. The liquid crystal molecules located on the surface of one of the first and second conducting layers have tilt angles, and liquid crystal molecules located on the surface of the other one of the first and second conducting layers don't have tilt angles. The first surface root-mean-square roughness is less than the second surface root-mean-square roughness.

The object of the present invention is to provide a curable resin composition which is excellent in cracking elongation rate, is low in arithmetic average roughness of an insulating layer surface in a wet roughing process, is also low in root mean square roughness, can form a plated and inlaid conductor layer having enough peel strength, and is also low in coefficient of linear thermal expansion. The curable resin composition provided by the present invention comprises a phenoxy resin (A) having an anthracene structure, an epoxy resin (B) and a curing agent (C),and is characterized in that the total quantity of the phenoxy resin (A), the epoxy resin (B) and the curing agent (C) is set as 100% by mass, the above phenoxy resin (A) is 1-15% by mass, and the epoxide equivalent of the above phenoxy resin (A) is more than 5000.

The invention discloses a protein antimicrobial catheter. A non-diffusivity nanoscale smooth coating is arranged on the surface of the material of the catheter body, the main ingredient of the coating is natural protein harmless to the human body, the thickness of the coating is 10 nm to 500 nm, and the RMS roughness of the coating is not larger than 100 nm. The invention further discloses a manufacturing method of the protein antimicrobial catheter. The method includes the main steps that the material of the catheter body is pre-processed, protein glue solution is prepared, the surface of the material of the catheter body is coated with the protein glue solution one time or multiple times, and finally the protein glue solution adhering to the surface of the material of the catheter body is cured with the method of natural curing or microwave curing or hot curing or ultraviolet curing or cross-linking curing or the like. The catheter manufactured with the method is excellent in bacteria resistance and antibacterial effects, economical burdens and body pains caused when a catheter is frequently replaced for a patient can be reduced, the catheter is good in stability and low in virulence in body, some discomfort symptoms will not be caused to the patient, and the catheter is safe in clinical use.

Disclosed is a mask blank substrate for use in lithography, wherein the main surface on which the transfer pattern of the substrate is formed has a root mean square roughness (Rms) of not more than 0.15 nm obtained by measuring an area of 1 μm×1 μm with an atomic force microscope, and has a power spectrum density of not more than 10 nm4 at a spatial frequency of not less than 1 μm−1.

A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base. Thus, a method of manufacturing a semiconductor wafer capable of efficiently manufacturing the semiconductor wafer regardless of the type of a base, and a composite base and a composite substrate suitably used in that manufacturing method are provided to efficiently manufacture a semiconductor device.

A rolling bearing for an inverter-driven motor has the thickness of an oil film in a steady operation condition stably maintained in a specific range, by which the withstand voltage can be controlled, and the discharge due to the shaft voltage of the inverter-driven motor is prevented and electrolytic corrosion can be suppressed. The rolling bearing for an inverter-driven motor has an inner ring, an outer ring, a rolling element, and grease, wherein a root mean square roughness of a raceway surface of at least one of the inner ring and the outer ring is 4 to 16 nm, and an oil film parameter Λ in steady operation is at least 17.5.