83 results about "XNOR gate" patented technology

The invention discloses a high-speed low-power-consumption dynamic comparator. The high-speed low-power-consumption dynamic comparator comprises a latch, an AND gate, a delay unit and an XNOR gate, wherein the latch is provided with first to third control ends; the output of the latch generates a first comparator output signal and a second comparator output signal through phase inverter I1 and I2 respectively; the first comparator output signal and the second comparator output signal generate an output signal through the XNOR gate; the output signal and a control signal clk1 are taken as input signals of the AND gate; an output signal of the AND gate controls a grid of a sixth NMOS (N-channel Metal Oxide Semiconductor) transistor P10; a delay signal clk2 of the clk1 is generated through the delay unit; and the clk2 is input into a third control end of the latch. According to the high-speed low-power-consumption dynamic comparator, the comparator output signals Dp and Dn generate the output signal through the XNOR gate, and the output signal and the control signal clk1 generate the control signal of the NMOS tube P10 through the AND gate, so that the problem of static power consumption in a conventional structure is solved.

A Class-D power amplifier having a distortion-suppressing function includes a gain control unit, a first PWM unit, a second PWM unit, a current control unit, and a level control unit. The level control unit includes at least one D flip-flop and at least one XNOR gate. The D flip-flop has an output end coupled with the gain control unit and an R end coupled with an output end of the XNOR gate. When the Class-D power amplifier has its positive output end and negative output end respectively and simultaneously outputting a high-level signal and a low-level signal to the XNOR gate, the XNOR gate outputs the high-level signal to the D flip-flop. Then the D flip-flop outputs the high-level signal to the gain control unit as feedback for controlling the gain control unit to reduce audio gain, thereby suppressing audio distortion.

The invention discloses a high-speed random number generation method and apparatus. The apparatus comprises two parts including an entropy source module and an entropy sampling module. The entropy source module is an autonomous Boolean network consisting of digital logic gates; the network consists of an XNOR gate and N-1 XOR gates; N is equal to 3n (n is a positive integer); and the entropy source module can generate a chaotic signal with a wide and flat spectrum. The entropy sampling module is composed of a D trigger, and performs sampling and quantization on the chaotic signal to generate arandom number sequence. The generated random number sequence can pass random number industry test standards (NIST and Diehard statistical tests), and has good random statistical characteristic. The apparatus consists of the digital logic gates, and is simple in circuit structure and easy to integrate and manufacture; and a post-processing algorithm or circuit necessary for a conventional random number generation apparatus is not required, so that the power consumption can be greatly reduced. The high-speed random number generation method and apparatus can be widely applied to the field of information security of secret communication, key distribution, data encryption and the like.

The invention relates to a full-gloss logic XNOR gate structure based on a micro-ring resonator structure, comprising a first nanowire waveguide, a second nanowire waveguide and a micro-ring resonant cavity, wherein the first nanowire waveguide and the second nanowire waveguide are parallel to each other, the micro-ring resonant cavity is positioned between the first nanowire waveguide and the second nanowire waveguide, gaps are respectively arranged between the micro-ring resonant cavity and the first nanowire waveguide and between the micro-ring resonant cavity and the second nanowire waveguide and ensure that the micro-ring resonant cavity satisfies critical coupling conditions so that light waves satisfying the resonant wavelength of the micro-ring resonant cavity can be completely coupled in the micro-ring resonant cavity through the first nanowire waveguide or the second nanowire waveguide, and the light extinction is realized on the output end of the first nanowire waveguide or the second nanowire waveguide. The invention utilizes the two-photon absorption effect in the micro-ring resonant cavity to realize the logic function of full-gloss 'XNOR'.

The invention discloses an optimum polarity search method for the design of a digital integrated circuit, which comprises the following steps: establishing a XNOR/OR circuit power consumption estimation model through optimizing the power consumption algorithm of a multi-input XNOR gate, so as to obtain the switching activity of the whole XNOR/OR circuit; utilizing the rapid list polarity conversion algorithm to realize conversion from the maximum item of a Boolean function to the XNOR/OR circuit expansion under the 0 polarity; carrying out the list technology-based polarity conversion algorithm according to the order of Gray code, so as to obtain the XNOR/OR circuit expansion under the other 2<N> minus 1 polarities; and finally obtaining the minimum power consumption, the minimum area and the minimum cost value and the optimum polarity of the XNOR/OR circuit. The invention has the advantages that the XNOR/OR logic circuit with the lower power consumption can be obtained; by measuring 10 MCNC Benchmark circuits, the XNOR/OR circuit corresponding to the optimum polarity searched via the method of the invention can save the switching activity and the area respectively by 94.4 percent and 82.2 percent at the most when comparing with the polarity 0,, and the 10 circuits can averagely save the witching activity and the area by 68.4 percent and 34.2 percent respectively.

The invention discloses a full-addition circuit composed of CMOS inverters and memristors. The full-addition circuit comprises four CMOS inverters, wherein the first inverter and four memristors forman XOR gate circuit, the fourth inverter and another four memristors form an XNOR gate circuit, the second inverter and the third inverter separately receive initial carry signals VCin, the upper endof the second inverter is connected to the input end of the first inverter, the lower end of the second inverter is connected to the input end of the fourth inverter, the second inverter outputs a carry signal VCout, the output end of the XOR gate circuit is connected to the upper end of the third inverter, the output end of the XNOR gate circuit is connected to the lower end of the third inverter, and the third inverter outputs a sum voltage VSum. The scheme of the invention has the effects that: according to the circuit, a logical circuit integrates computing and storage functions, logical operation steps can be greatly reduced, components required by the circuit can be simplified, the circuit costs can be further reduced, and the integration degree of the circuit can be improved.

The invention discloses an XOR/XNOR gate circuit based on FinFET devices. The circuit comprises a first FinFET transistor, a second FinFET transistor, a third FinFET transistor, a fourth FinFET transistor, a fifth FinFET transistor, and a sixth FinFET transistor, the first FinFET transistor and the fourth FinFET transistor are both P-type FinFET transistors, the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all N-type FinFET transistors, the first FinFET transistor and the fourth FinFET transistor are both low-threshold FinFET transistors, the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all high-threshold FinFET transistors, the numbers of the fins of the first FinFET transistor and the fourth FinFET transistor are both 1, and the numbers of the fins of the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all 2. The circuit is advantageous in that the logic function is correct, the circuit area is small, the time delay is short, the power consumption is low, and the consumption-delay product is small.

The invention relates to a digital in-memory computing array device, which comprises 256 row * 64 column in-memory computing modules, each in-memory computing module comprises a bit cell, a tube T7, a tube 8 and an XNOR gate, and the tube T7 and the tube 8 form a transmission gate; the weight storage point Q of the bit cell is connected with the input end of the transmission gate, the output end of the transmission gate is connected with the first input end of the XNOR gate, the second input end of the XNOR gate is connected with an input signal, the output of the XNOR gate serves as the output of the bit cell, the grid electrode of the tube T7 is connected with a control signal RE, and the grid electrode of the tube T8 is connected with a control signal REN; an input signal input by each bit unit and the weight storage point Q are subjected to XNOR operation through an XNOR gate; and a column of bit cells is calculated each time, and thus accumulating 1bit outputs of 256 bit cells and then outputting a 9bit multiply-accumulate result. According to the invention, the calculation precision is improved.

The invention relates to an all-optical logic gate with a Michelson structure, which can be reused for realizing an AND gate, an OR gate, an NOT gate, an NAND gate, an NOR gate, an XOR gate and an XNOR gate as well as the reverse operation thereof, and also realizing a half-adder. The all-optical logic gate with a Michelson structure comprises two control optical signals, a synchronous optical detection signal and an output detection signal, wherein the two control optical signals are input into an arm (2) of symmetrical Michelson interferometers by a coupler (1); the synchronous optical detection signal is divided into two beams of equal light to be projected into the arm (2) and an arm (3) of the Michelson interferometers and used for outputting a reflecting output opening (4) for expressing the application of the logic result and a transmitting output opening (5) of the reverse operation; the output detection signal is results of the self-phase modulation of a detection optical signal, the intersection phase modulation of the two control optical signals on detection light and average intersection phase modulation on the detection light in two times of arm length and is expressed into a corresponding logic gate relation. The all-optical logic gate has the characteristic of self-phase modulation in the symmetrical Michelson interferometers, preferably the two arms adopt different nonlinear optical fibers and the input arm (2) of the control optical signals adopts a high nonlinear optical fiber.

The invention provides a synchronous control signal generating circuit. The generating circuit comprises a PWM module 1, a PWM module 2, a power-on time delay circuit, a D trigger U1, a D trigger U2, an electric control switch S1, an electric control switch S2, a three-state gate G1, an XNOR gate G2, an XNOR gate G3, an OR gate G4, and a synchronous signal syn input-output connection terminal; the generating circuit adopts the non-master-slave and dynamic synchronization scheme, and has higher reliability in comparison with the static master-slave synchronization scheme; a synchronous clock signal source is produced through a competition way in the parallel control, the synchronous clock signal source is from the module with the three-state gate being at the on-state at the earliest in the synchronous control signal generating circuit, so that the synchronous signal source is unique. The generating circuit provided by the invention supports the hot-plugging under the parallel system working condition and cannot lose the synchronous signal. Compared with the synchronous control scheme performed through a communication bus, the synchronous control signal generating circuit has the advantage that the synchronization of the controller can be realized by only using a conductor to connect, the structure is simple and practicability is good.

The invention discloses a clock switching structure having an automatic resetting function. The clock switching structure comprises a pulse generating circuit M1, a clock switching circuit M2, and a resetting generating circuit M3. The pulse generating circuit M1 is used for monitoring changing of a clock selection signal CS, and comprises three D triggers triggered by a rising edge of a clock and an XNOR gate. The clock switching circuit M2 is used to switch an output clock between a clock source CLK1 and a clock source CLK2, which are different from each other, and comprises a D trigger D4 used for triggering a rising edge of an enabling end, two two-input AND gates, and a two-input OR gate. The resetting generating circuit M3 is used to generate and eliminate a resetting signal automatically, and comprises three D triggers triggered by a rising edge provided with an asynchronous clearing end and a phase inverter INV. The clock switching structure is advantageous in that only the clock selection signal is required to be provided, and when the clock selection signal is changed, the resetting signal is generated automatically, and the clock switching is carried out; after the switching is completed, the resetting signal is eliminated after a certain period, and a controlled circuit can work normally.

The embodiments of the invention provide a XNOR gate circuit, a regulating method and an XOR gate circuit, and relates to the field of logic circuits. The XNOR gate circuit includes a first input module, a second input module, an output module and a time-delay module. An input end of the first input module is in electrical connection to a first signal source. A first output end of the first inputmodule and a first end of the time-delay module are in electrical connection. A second output end of the first input module and one end of the output module are in electrical connection. An input endof the second input module is in electrical connection to a second signal source. An output end of the second input module and a second end of the time-delay module are in electrical connection. A third end of the time-delay module and the other end of the output module are in electrical connection. The time-delay module is intended for when a first signal is faster than a second signal by T time,postponing the first signal for T time, such that the first signal that is postponed for T time is synchronous with the second signal so as to acquire an output signal from the other end of the output module. The XNOR gate circuit prevents the output signal from having blurr.

Provided are a neural network circuit device, a neural network, a neural network processing method, and a neural network execution program, each of which does not require a bias. A binarized neural network circuit includes: an input part configured to allow input of an input node which allows input of input values x1-xn (xi) (binary), and input of weights w1-wn (wi) (binary); an XNOR gate circuit configured to receive the input values x1-xn and the weights w1-wn and to take XNOR logic; a sum circuit configured to sum XNOR logical values; a batch normalization circuit configured to correct a variance due to binarization, by extending a range of normalization and shifting a center thereof; and an activating function circuit configured to convert a signal B obtained by batch-normalizing a signal Y generated by taking the sum, by means of an activating function f sgn(B).

An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates ‘odd’ parity, and to pass the redundant data value to the output when the parity engine output indicates ‘even’ parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.

The invention discloses a hardware fault diagnosis circuit and method, and a mainboard. The circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an XNOR gate, a first watchdogchip and a second watchdog chip. For the problem of jamming due to hardware initialization failure, an effective solution is given; through cooperation of BIOS software, BMC software and hardware, hardware faults can be automatically diagnosed for whether BMC Boot loader-based hardware initialization failure or BIOS-based hardware initialization failure in whether a development stage or a user scene; locating is accurate; convenience and quickness are achieved; each mainboard can be covered; and small-probability faults can be solved.