103results about How to "Reduce bit width" patented technology

A communication system has lighting equipment that has transmitter comprising multiple light-emitting elements that each emit light of different wavelengths and terminal equipment that has light-receiver comprising multiple light-receiving elements that receive optical signals for each of the different wavelengths.

The invention discloses a platform histogram equalization realization method based on an FPGA, and d device thereof. When frames are effective, a histogram statistic module carries out histogram statistics on the data of a number t frame of image, an RAM reading-writing control module process a statistical histogram according to a set upper limit platform value, and the processed statistical histogram is input into the RAM; after the data of the number t frame of image is counted, a reading signal of the RAM is generated by an RAM reading control module, the reading signal is sent to the RAM through the RAM reading-writing control module, the read statistical histogram is sent to a histogram accumulation module, the histogram accumulation module accumulates the statistical histogram, and the accumulated statistical histogram is written into an SDRAM through an SDRAM arbitration control module; and when the data of a number (t+1) frame of image is effective, the above operation on the statistical histogram is repeated, and a platform histogram output module reads the accumulated histogram of the number t frame of image through the SDRAM, calculates the number (t+1) frame of image after equalization and outputs the image. According to the invention, a large number of internal resources of the FPGA are saved, the power consumption of the FPGA is reduced, and the operation speed is improved.

The invention provides a calculation method and device applied to neural networks. The calculation method comprises the following steps of: obtaining a binary convolutional kernel which only comprisesa numerical value 1 and a -1 weight; decomposing the binary convolution kernel into an initial convolution kernel and a feature convolutional kernel, wherein the initial convolution kernel and the feature convolution kernel are same as the binary convolution kernel in the aspect of dimensionality, the initial convolution kernel is a matrix formed by a weight with a numerical value of 1, and the feature convolution kernel is a matrix formed by a weight with a numerical value of -1 relative to the binary convolution kernel; and carrying out convolution calculation in a neural network on the basis of the initial convolution kernel and the feature convolution kernel. By utilizing the calculation method and device provided by the invention, the convolution calculation efficiency can be improved and the storage circuit overhead can be saved.

A timing controller for a display apparatus includes a dithering unit outputting a first signal in which bit widths of image signals are reduced, an image pattern detector detecting an image pattern of the image signals and outputting a dithering off signal corresponding to the detected image pattern, a dithering selector receiving the first signal and converts the first signal to a second signal in response to the dithering off signal, and a response time compensator generating a present image signal from the second signal and compensates a liquid crystal response time in accordance with a difference between the present image signal and a first previous image signal to output a data signal.

The embodiment of the invention discloses an intelligence quotient (IQ) data transmission method, which comprises the following steps that: s sample pints in a single-antenna single-carrier container block in IQ data to be transmitted are divided into p data blocks, and each data block comprises q sample points; the public index part exp of the q sample points in each data block, the exponential function f(exp) and the respective mantissa parts are respectively determined; the public index parts of the q sample points in each data block and the respective mantissa parts are respectively mapped into the corresponding data block; and p data blocks are transmitted through common public radio interface (CPRI) frames. When the embodiment of the invention is adopted, the s sample points are divided into p data blocks, each data block comprises the q sample points, the q sample points are determined into the public index part, the exponential function and the respective mantissa parts and are then mapped into the data block, the bit width required by the data transmission can be reduced, and the data transmission efficiency is improved.

A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist by replacing memory with substitute nodes representing selected slots in the memory, segmenting word level nodes, including one or more of the substitute nodes, in the netlist into segmented nodes, finding reduced safe sizes for the segmented nodes and generating an updated data structure representing the circuit design using the reduced safe sizes of the segmented nodes. The correctness of such systems can require reasoning about a much smaller number of memory entries and using nodes having smaller bit widths than exist in the circuit design. As a result, the computational complexity of the verification problem is substantially reduced.

A digital sigma-delta modulator requiring minimal die area and dissipating minimal power is formed with a plurality of integration stages coupled in tandem between an input node and an output node. The bit width of signals in the integration stages is progressively reduced from the first to the last integration stage without compromising modulator accuracy. A quantizer between the last integration stage and the output node provides the final reduction of signal bit width. The gain of the modulator feedforward and feedback paths are integer powers of two to further simplify the digital computation. In an exemplary implementation, three integration stages to form a third-order modulator are coupled in tandem between the input node and the output node. The gains of feedback and feedforward paths in one preferred embodiment are unity, and in some embodiments, one feedforward path has gain of 0.5.

A variable-mode digital logic circuit is provided for accepting and serializing a parallel data word, so that the parallel data word may be transmitted from the digital logic circuit over a single one-bit wide trace. In some embodiments, the variable-mode digital logic circuit may include a plurality of parallel data traces for receiving the parallel dataword, a plurality of select-capable multiplexor circuits for sequentially activating certain ones of the parallel data traces and for multiplexing the received data into a serial data stream, a ring counter for controlling a frequency of specific operations performed within the circuit, and at least one additional multiplexor circuit array for receiving data output from the plurality of select-capable multiplexor circuits and for further serializing the received data for output on the single one-bit wide trace. The digital logic circuit may be adapted to operate according to one of a plurality of variable modes.

The invention discloses a sampling rate conversion filter and a sampling rate conversion achieving method. The filter comprises a filtering module used for conducting filtering processing on input signals, a first in first out (FIFO) module, a control module and a delay processing module. The FIFO module is used for writing signal data of each stage under control of the control module and conducting rate and clock domain conversion. The control module is used for controlling the delay processing module to read converted signal data of each stage and generating delay parameter. The delay processing module is used for reading converted signal data of each stage, adding the signal data of each stage and signal data of the previous stage subjected to position-cutting processing, multiplying the obtained sum with the delay parameter, conducting position-cutting processing on signal data obtained by multiplying and then transmitting the signal data to the next stage. Output signals are obtained till the last stage of signal data is processed. The filter reduces data processing amount through the position-cutting processing, reduces system resource occupation quantity, ensures time sequence through the FIFO unit and improves processing performance of the filter.

An apparatus for low density parity check decoding includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node messages and to calculate checksums based on the variable node to check node messages, and a scheduler operable to determine a layer processing order for the variable node processor and the check node processor based at least in part on the number of unsatisfied parity checks for each of the H matrix layers.

The invention discloses a method and device for intercepting a baseband signal. The method comprises the following steps of: performing signal processing on the baseband signal to obtain an amplitude delay profile (ADP) set; intercepting a bit where the maximum value of the energy path of the ADP set is positioned and 8-12 bits below the bit by taking the maximum value of an energy path detected by adopting a previous threshold as an intercepting parameter to obtain sampled data; or intercepting a bit where the average noise value of the ADP set is positioned and 8-12 bits above the bit by taking an average noise value detected by adopting the previous threshold as the intercepting parameter to obtain sampled data. By adopting the method and the device, the bit width of the signal can be reduced, the effect of reducing chip storage space and power consumption is achieved and the chip cost is saved. If 8 bits are intercepted from one sampled datum, storage space is saved by one time compared with the conventional way for storing two 8-bit RAMs (Random Access Memories) within 12-16 bits.

The invention discloses a signal processing method. The method comprises the following steps: carrying out equalization processing on a to-be-processed signal through a first forward feedback equalizer FFE to obtain a first signal; determining a second signal through a judgment rule according to the first signal and the preset signal, the preset signal being used for providing a judgment standard,the judgment rule indicating a judgment relationship between the first signal and the preset signal, and the judgment rule being used for judging the first signal as a target level or position information according to the preset signal; performing equalization processing on the second signal through a nonlinear model or through a second forward feedback equalizer to obtain a third signal; and obtaining an output signal according to the first signal and the third signal. According to the method, the interference of the signal is processed in two parts, the residual ISI or nonlinear interference can be eliminated in a mode of matching hard decision with the FFE or nonlinear model, the interference elimination performance of the system can be basically stable by using less resource cost, andthe purpose that less resources have the maximum performance is achieved.

A radar sensing system for a vehicle includes transmitters, receivers, a memory, and a processor. The transmitters transmit radio signals and the receivers receive reflected radio signals. The processor produces samples by correlating reflected radio signals with time-delayed replicas of transmitted radio signals. The processor stores this information as a first radar data cube (RDC), with information related to signals reflected from objects as a function of time (one of the dimensions) at various distances (a second dimension) for various receivers (a third dimension). The first RDC is processed to compute velocity and angle estimates, which are stored in a second RDC and a third RDC, respectively. One or more memory optimizations are used to increase performance. Before storing the second RDC and the third RDC in an internal / external memory, the second and third RDCs are sparsified to only include the outputs in specific regions of interest.

The invention relates to the technical field of image processing, in particular to an image processing method and device, computer equipment and a storage medium. The method comprises the steps of obtaining a to-be-processed target image; obtaining a neural network model, wherein the neural network model is used for discretizing the floating point type data in different data ranges by adopting different discretization modes to obtain corresponding integer data with a preset bit width; and calling the neural network model to process the target image, and outputting to obtain image feature data.According to the embodiment of the invention, the bit width of integer data is effectively controlled in the floating point type data integer process, the storage representation range of the integerdata is expanded, namely, low-bit-width and high-precision integer is realized, and meanwhile, calculation acceleration is realized due to the speed advantage and the resource advantage of fixed-pointnumber operation, so that the image processing efficiency and the subsequent image feature extraction effect are improved.