Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate

Abstract

The invention discloses a circuit capable of realizing multiplexing of an exclusive-OR gate or an XNOR gate, belonging to the technical field of integrated circuits. The circuit comprises a compound logic gate circuit and an either-or gating circuit which are cascaded; the compound logic gate circuit comprises a NOR gate unit, an AND-OR-NOT gate unit and a first phase inverter, an input end of the NOR gate unit and the input end of the AND-OR-NOT gate unit are respectively connected with two paths of input signals, an output end of the NOR gate unit is connected with a control end of the AND-OR-NOT gate unit, the output end of the AND-OR-NOT gate unit is connected with the input end of the first phase inverter and outputs an exclusive-OR operation result, and the output end of the first phase inverter outputs an XNOR operation result; and the either-or gating circuit performs gating on an exclusive-OR gate unit composed of the NOR gate unit and the AND-OR-NOT gate unit, or an XNOR gate unit composed of the NOR gate unit, the AND-OR-NOT gate unit and the first phase inverter. The circuit provided by the invention realizes simple multiplexing of the exclusive-OR gate or XNOR gate circuit, reduces the number of transistors of the whole circuit system, and consequently reduces the layout area and circuit power consumption.

Description

technical field [0001] The invention discloses a circuit capable of realizing the multiplexing of the exclusive OR gate or the same OR gate, and belongs to the technical field of integrated circuits. Background technique [0002] In the encryption and decryption operations in the field of integrated circuits, XOR gates and NOR gates are widely used logic gate circuits, which makes them occupy a considerable part of the area on the circuit layout. The invention whose application number is 200510075399.0 designs an AES encryption and decryption circuit optimization method and multiplexes Sbox modules, which reduces the circuit scale and reduces circuit power consumption and area by making the encryption and decryption circuits share one Sbox module; the existing encryption and decryption operation circuits Most of them use separate XOR gates or XOR gates, and there are few circuits that realize XOR gates or XOR gates. It is urgent to design a reusable logic gate circuit, so t...

AI Technical Summary

Problems solved by technology

The invention whose application number is 200510075399.0 designs an AES encryption and decryption circuit optimization method and multiplexes Sbox modules, which reduces the circuit scale and reduces circuit power consumption and area by making the encryption and decryption circuits share one Sbox module; the existing encryption and decryption operation circuits Most of them use separate XOR gates or XOR gates, and there are few circuits that implement XOR gates or XOR gates.

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