178 results about "Transistor count" patented technology

A NOR gate includes is constructed with two asymmetric FinFET type transistors instead of the conventional four-transistor NOR gate. The reduction in the number of transistors from four down to two allows for significant improvements in integrated semiconductor circuits.

A plurality of pixel groups X(n) each comprising a plurality of pixels are set, and switched capacitor amplification parts are provided in correspondence to the pixel groups, respectively. Each of the switched capacitor amplification parts has a charge detection node to which output terminals of the transfer transistors of a corresponding pixel group X(n) are connected in common, an amplification part, a reset transistor, a first capacitance element, and a select transistor. A load part common to the switched capacitor amplification parts is provided. The load part is combined with the amplification parts of the switched capacitor amplification parts to constitute inverting amplifiers, respectively. By means of the above constitution, it is capable of obtaining a noise-reduced, high-quality image and which allows transistor count per pixel to be cut, thus allowing the pixel size to be reduced.

A multi-ported register cell that reduces the number of metal wires and/or transistors per write port. The cell includes a storage element that stores a bit. Each write port includes three transistors and two wires. The first transistor is coupled to a true input of the storage element. The second transistor is coupled to a complement input of the storage element. The first wire selectively turns on the first and second transistors of one of the ports. The second wire provides the update value. The third transistor selectively couples the second transistor to ground depending upon whether the second wire turns on the third transistor, thereby providing a complement of the update value to the second transistor. The cell also includes one or more read ports for reading the storage element bit. A multi-ported register file may be created from the cells.

The invention provides a shifting register unit, a driving method, a grid drive circuit and a display device. The shifting register unit comprises a pull-up node control subunit, a pull-down node control subunit and an output subunit, wherein the output subunit comprises N output modules, an nth output module controls an nth grid drive signal output end to be connected with an nth clock signal output end under control of a pull-up node in an output phase, the nth grid drive signal output end is controlled to output a second electric level in an nth output time segment of the output phase, and n is a positive integer which is less than or equal to N. The shifting register unit can help solve a problem that a conventional grid drive circuit is large in transistor quantity, and a narrow frame cannot be easily realized.

The invention discloses a low-power-consumption xor/xnor gate circuit which is characterized by comprising an input inverter module, a complementary transmission tube logic module and a differential series voltage switch logic module. The input inverter module is connected with the complementary transmission tube logic module which is further connected with the differential series voltage switch logic module. The low-power-consumption xor/xnor gate circuit has the advantages that transistors of the circuit are reduced without affecting circuit performances, so that power consumption of the circuit is effectively reduced. Further, the low-power-consumption xor/xnor gate circuit not only has xor logic functions but also has xnor logic functions.

A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

Circuits for performing four terminal measurement point (TMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a semiconductor chip. The circuit includes a DUT having a first terminal and a second terminal, where the first terminal of the DUT is connectable to a first terminal measurement point and a third terminal measurement point, and the second terminal of the DUT is connectable to a second terminal measurement point and a fourth terminal measurement point. A first transistor is provided to select access to the first terminal measurement point, a second transistor is provided to select access to the third terminal measurement point, a third transistor is provided to select access to the second terminal measurement point; and a fourth transistor is provided to select access to the fourth terminal measurement point. In one example, the DUT is linked to neighboring DUTs, and selected ones of the first through fourth transistors are shared, thus reducing the number of transistors per DUT in a DUT bank, and reducing the area needed to implement DUT bank testing for addressable 4-TMP testing. The compact circuitry further enables DUT bank stacking in rows, addressing of columns of DUTs for conditional testing, and three dimensional stacking of DUT banks on different levels.

The invention discloses a low-power-consumption short pulse generation circuit and a low-power-consumption pulse type D trigger. The low-power-consumption short pulse generation circuit is characterized by comprising a first P-channel metal oxide semiconductor field effect transistor (PMOSFET), a first N-channel MOSFET (NMOSFET), a first NAND gate and a first phase inverter. The low-power-consumption pulse type D trigger is characterized by comprising the low-power-consumption short pulse generation circuit, an input phase inversion circuit, a clock control complementary MOS (CMOS) logic D latch unit and an output phase inversion circuit. The invention has the advantages that: under the condition of no influence of the performance of the circuit, the quantity of the transistors of the circuit is small; the structure is simpler; and the power consumption of the circuit is effectively reduced.

An embodiment relates to an organic light emitting display device that has a simple structure and compensate threshold voltage of a driving transistor.

The organic light emitting display device that operates in an initializing period, a scan period, and an emission period divided from one frame, includes: first pixels positioned in odd-numbered vertical lines; second pixels positioned in even-numbered vertical lines; first scan lines and second scan lines formed horizontal lines and coupled with the second pixels; third scan lines and fourth scan lines formed in the horizontal lines and coupled with the first pixels; and a scan driver driving the first scan lines and the fourth scan lines, in which the number of transistors in the first pixels is different from the number of transistors in the second pixels.