Low-power-consumption short pulse generation circuit and low-power-consumption pulse type D trigger

Abstract

The invention discloses a low-power-consumption short pulse generation circuit and a low-power-consumption pulse type D trigger. The low-power-consumption short pulse generation circuit is characterized by comprising a first P-channel metal oxide semiconductor field effect transistor (PMOSFET), a first N-channel MOSFET (NMOSFET), a first NAND gate and a first phase inverter. The low-power-consumption pulse type D trigger is characterized by comprising the low-power-consumption short pulse generation circuit, an input phase inversion circuit, a clock control complementary MOS (CMOS) logic D latch unit and an output phase inversion circuit. The invention has the advantages that: under the condition of no influence of the performance of the circuit, the quantity of the transistors of the circuit is small; the structure is simpler; and the power consumption of the circuit is effectively reduced.

Description

technical field [0001] The invention relates to a short pulse generating circuit, in particular to a low power consumption short pulse generating circuit and a low power consumption pulse type D flip-flop. Background technique [0002] In recent decades, portable electronic devices have been widely used in the fields of consumer electronics, medical equipment and industrial instruments, and integrated circuits, as the core part of portable electronic devices, have developed rapidly. In the past integrated circuit design, the operating speed and area of ​​the chip are the main factors considered by the designer, and the power consumption problem is often ignored. With the continuous development of the semiconductor manufacturing industry, while the integration density and operating frequency of the circuit are gradually increasing, the dynamic power consumption and leakage power consumption of the chip are also increasing (see the literature Malay Ranjan Tripathy, "Nano CMOS"...

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Problems solved by technology

Shinichi Kozu, Masayuki Daito, Yukinori Suglyama and others proposed a short pulse generation circuit with an AND gate structure. By making the clock signal and the complementary clock signal at the two input terminals of the AND gate be high at the same time in a short period of time, Thus, a short pulse signal is generated, and multiple inverters are cascaded at the output of the AND gate. Although a complementary clock signal with sufficient delay can be obtained, it also increases the number of circuit transistors and the power consumption of the circuit.

like figure 2 As shown, the short pulse generating circuit is composed of a PMOS transistor, an NMOS transistor, an AND gate and two inverters, wherein the AND gate is composed of a NAND gate and an inverter, and the The NAND gate is composed of two PMOS transistors and two NMOS transistors. The two PMOS transistors and the two NMOS transistors are all transistors with the minimum channel length under the standard process, but the NAND gate based on this structure has a short The pulse generation circuit needs to use multiple inverters to generate short pulse signals with sufficient pulse width. The increase of inverters leads to an increase in the number of transistors in the circuit, which leads to an increase in power consumption of the circuit

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