Power consumption optimizing method for mixed polarity XNOR/OR circuit

Abstract

The invention discloses a power consumption optimizing method for a mixed polarity XNOR / OR circuit. The method comprises the following steps: improving a quick list technology according to the characteristics of an expression of the mixed polarity XNOR / OR circuit, so as to realize the mixed polarity conversion of the XNOR / OR circuit; on the basis of a power consumption estimation model, utilizing a Hoffman algorithm to realize the low power consumption decomposition of an OR gate, and dividing input signals of a multi-input XNOR gate into three sets according to the distribution characteristics of input signal probability and output signal probability of a two-input XNOR gate, wherein the three sets are as follows: the input signal probability being more than 0.5, the input signal being less than 0.5 and the input signal being equal to 0.5; synthesizing in each set, realizing the low power consumption decomposition of the multi-input XNOR gate and synthesizing the low power consumption decomposition of the OR gate and that of the multi-input XNOR gate, thereby obtaining a mixed polarity fitness function; establishing a corresponding relation between the mixed polarity and particle swarm; and adopting a particle swarm optimizing algorithm for performing the optimized power consumption mixed polarity searching on the XNOR / OR circuit. The power consumption optimizing method has the advantages that a test for a MCNC Benchmark circuit shows that the corresponding circuit power consumption is averagely saved for 53.98% and the searching speed is obviously increased.

Description

technical field [0001] The invention relates to a method for optimizing power consumption of circuits in integrated circuit design, in particular to a method for optimizing power consumption of mixed polarity and / or circuits. Background technique [0002] The continuous improvement of the operating frequency and integration of integrated circuits leads to higher and higher total power consumption of the circuit. The sharply rising power consumption increases the production, packaging and heat dissipation costs of the system, and also has a great impact on the reliability of the system. . Low power consumption has become one of the important goals in very large scale integration (VLSI) design, especially in portable devices, where low power consumption has surpassed area and performance as the primary design constraint. Most of the current research on low-power technology is aimed at AND / OR (AND / OR) and NAND / XOR (NAND / NOR) circuits. The typical implementation is to generate ...

AI Technical Summary

Problems solved by technology

The huge polar search space of the MPRM circuit also leads to the time and space complexity of its circuit performance optimization being higher than that of the FPRM circuit. Therefore, a new breakthrough is urgently needed in the optimization theory and solution method of the MPRM logic circuit

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