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XOR/XNOR gate circuit based on FinFET devices

A gate circuit and device technology, applied in the direction of exclusive-OR circuit, logic circuit with logic function, logic circuit, etc., can solve the problems of device instability, limiting circuit performance, large circuit leakage power consumption, etc., to reduce delay Effect

Active Publication Date: 2016-06-29
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] With the continuous reduction of transistor size, limited by the short channel effect and the current manufacturing process, the space for reducing the size of ordinary CMOS transistors is extremely narrow
When the size of ordinary CMOS transistors is reduced to below 20nm, the leakage current of the device will increase sharply, resulting in large leakage power consumption of the circuit
Moreover, the short-channel effect of the circuit becomes more obvious, and the device becomes quite unstable, which greatly limits the improvement of the circuit performance

Method used

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  • XOR/XNOR gate circuit based on FinFET devices
  • XOR/XNOR gate circuit based on FinFET devices
  • XOR/XNOR gate circuit based on FinFET devices

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0016] Embodiment one: if figure 2 As shown, an XOR / XOR gate circuit based on FinFET devices includes a first FinFET tube M1, a second FinFET tube M2, a third FinFET tube M3, a fourth FinFET tube M4, a fifth FinFET tube M5 and a sixth FinFET tube M5. The FinFET tube M6, the first FinFET tube M1 and the fourth FinFET tube M4 are all P-type FinFET tubes, the second FinFET tube M2, the third FinFET tube M3, the fifth FinFET tube M5 and the sixth FinFET tube M6 are all N-type FinFET tubes tube; the first FinFET tube M1 and the fourth FinFET tube M4 are both low-threshold FinFET tubes, the second FinFET tube M2, the third FinFET tube M3, the fifth FinFET tube M5 and the sixth FinFET tube M6 are all high-threshold FinFET tubes, The number of fins of the first FinFET tube M1 and the fourth FinFET tube M4 is 1, and the number of fins of the second FinFET tube M2, the third FinFET tube M3, the fifth FinFET tube M5 and the sixth FinFET tube M6 is 2;

[0017]Both the source of the firs...

Embodiment 2

[0018] Embodiment two: if figure 2 As shown, an XOR / XOR gate circuit based on FinFET devices includes a first FinFET tube M1, a second FinFET tube M2, a third FinFET tube M3, a fourth FinFET tube M4, a fifth FinFET tube M5 and a sixth FinFET tube M5. The FinFET tube M6, the first FinFET tube M1 and the fourth FinFET tube M4 are all P-type FinFET tubes, the second FinFET tube M2, the third FinFET tube M3, the fifth FinFET tube M5 and the sixth FinFET tube M6 are all N-type FinFET tubes tube; the first FinFET tube M1 and the fourth FinFET tube M4 are both low-threshold FinFET tubes, the second FinFET tube M2, the third FinFET tube M3, the fifth FinFET tube M5 and the sixth FinFET tube M6 are all high-threshold FinFET tubes, The number of fins of the first FinFET tube M1 and the fourth FinFET tube M4 is 1, and the number of fins of the second FinFET tube M2, the third FinFET tube M3, the fifth FinFET tube M5 and the sixth FinFET tube M6 is 2;

[0019] Both the source of the fir...

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PUM

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Abstract

The invention discloses an XOR / XNOR gate circuit based on FinFET devices. The circuit comprises a first FinFET transistor, a second FinFET transistor, a third FinFET transistor, a fourth FinFET transistor, a fifth FinFET transistor, and a sixth FinFET transistor, the first FinFET transistor and the fourth FinFET transistor are both P-type FinFET transistors, the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all N-type FinFET transistors, the first FinFET transistor and the fourth FinFET transistor are both low-threshold FinFET transistors, the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all high-threshold FinFET transistors, the numbers of the fins of the first FinFET transistor and the fourth FinFET transistor are both 1, and the numbers of the fins of the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all 2. The circuit is advantageous in that the logic function is correct, the circuit area is small, the time delay is short, the power consumption is low, and the consumption-delay product is small.

Description

technical field [0001] The invention relates to an XOR / XOR gate circuit, in particular to an XOR / XOR gate circuit based on a FinFET device. Background technique [0002] The basic logic circuit is the most basic logic circuit in the digital circuit, and the XOR / XOR gate circuit is an indispensable part of the basic logic circuit. The dual-rail logic of differential cascaded voltage switching logic provides differential output, but traditional voltage switching logic still faces the problems of large number of transistors, large power consumption and complex design. With the continuous advancement of VISL technology, the operating speed and power consumption requirements of digital systems continue to increase, and the performance requirements for basic logic units are also more stringent, requiring that basic logic units should have low power consumption and short delay. [0003] As the size of transistors continues to shrink, limited by the short-channel effect and the cur...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/21H03K19/20
CPCH03K19/20H03K19/215
Inventor 胡建平张绪强
Owner NINGBO UNIV
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