High-speed low-power-consumption dynamic comparator

Abstract

The invention discloses a high-speed low-power-consumption dynamic comparator. The high-speed low-power-consumption dynamic comparator comprises a latch, an AND gate, a delay unit and an XNOR gate, wherein the latch is provided with first to third control ends; the output of the latch generates a first comparator output signal and a second comparator output signal through phase inverter I1 and I2 respectively; the first comparator output signal and the second comparator output signal generate an output signal through the XNOR gate; the output signal and a control signal clk1 are taken as input signals of the AND gate; an output signal of the AND gate controls a grid of a sixth NMOS (N-channel Metal Oxide Semiconductor) transistor P10; a delay signal clk2 of the clk1 is generated through the delay unit; and the clk2 is input into a third control end of the latch. According to the high-speed low-power-consumption dynamic comparator, the comparator output signals Dp and Dn generate the output signal through the XNOR gate, and the output signal and the control signal clk1 generate the control signal of the NMOS tube P10 through the AND gate, so that the problem of static power consumption in a conventional structure is solved.

Description

technical field [0001] The invention belongs to the technical field of analog or digital-analog mixed integrated circuits, and in particular relates to a high-speed and low-power dynamic comparator. Background technique [0002] In recent years, with the continuous development of integrated circuit manufacturing technology, the feature size of CMOS devices has been continuously reduced, and the operating voltage of integrated circuits has also been continuously reduced. Under the deep submicron process, the working speed of analog-to-digital converters has been greatly improved. Improve, at the same time, power consumption is further reduced. However, as the core component of the analog-to-digital converter, the performance of the comparator has become a bottleneck in the design of high-speed and low-power consumption. Several traditional comparator structures are difficult to meet the requirements of speed, power consumption and low power supply voltage at the same time. ...

AI Technical Summary

Problems solved by technology

However, as the core component of the analog-to-digital converter, the performance of the comparator has become a bottleneck for high-speed and low-power designs

Several traditional comparator structures are difficult to meet the requirements of speed, power consumption and low power supply voltage at the same time

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