A High Speed ​​Low Power Dynamic Comparator

Abstract

The invention discloses a dynamic comparator with high speed and low power consumption, which includes a latch, an AND gate, a delay unit, and an NOR gate. The latch has first to third control terminals, and the outputs of the latches respectively pass through inverters. I1 and I2 generate the first comparator output signal and the second comparator output signal, the first comparator output signal and the second comparator output signal generate an output signal through the NOR gate, this output signal and the control signal clk1 are used as the AND gate The input signal, the output signal of the AND gate controls the gates of the six NMOS transistors P10, clk1 generates its delayed signal clk2 through the delay unit, and clk2 is input to the third control terminal of the latch. The present invention uses the comparator output signals Dp and Dn to generate an output signal through the same OR gate XNOR, and the output signal and the control signal clk1 pass through the AND gate to generate the control signal of the NMOS transistor P10, which solves the problem of static power consumption in the traditional structure.

Description

technical field [0001] The invention belongs to the technical field of analog or digital-analog mixed integrated circuits, and in particular relates to a high-speed and low-power dynamic comparator. Background technique [0002] In recent years, with the continuous development of integrated circuit manufacturing technology, the feature size of CMOS devices has been continuously reduced, and the operating voltage of integrated circuits has also been continuously reduced. Under the deep submicron process, the working speed of analog-to-digital converters has been greatly improved. Improve, at the same time, power consumption is further reduced. However, as the core component of the analog-to-digital converter, the performance of the comparator has become a bottleneck in the design of high-speed and low-power consumption. Several traditional comparator structures are difficult to meet the requirements of speed, power consumption and low power supply voltage at the same time. ...

AI Technical Summary

Problems solved by technology

However, as the core component of the analog-to-digital converter, the performance of the comparator has become a bottleneck for high-speed and low-power designs

Several traditional comparator structures are difficult to meet the requirements of speed, power consumption and low power supply voltage at the same time

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