FPGA high-performance interconnection circuit

Abstract

The invention discloses an FPGA high-performance interconnection circuit, and relates to an integrated circuit technology. The circuit comprises i secondary NMOS tubes connected in parallel, wherein the output end of each secondary switch NMOS tube is connected to a common reference point; the input end of each secondary NMOS transistor is connected with a primary NMOS transistor group, the primary NMOS transistor group is composed of m primary NMOS transistors which are connected in parallel, the output end of each primary NMOS transistor in the same primary NMOS transistor group is connectedwith the corresponding secondary NMOS transistor, and the input end of each primary NMOS transistor in the same primary NMOS transistor group is used as the input end of the interconnection circuit;in each primary NMOS tube group, the primary NMOS tubes with the same serial number are controlled by the same primary SRAM unit, and each secondary NMOS tube is connected to the corresponding secondary SRAM; wherein the common reference point is connected to the output end through the pull-up circuit and the level recovery circuit, and i and m are integers greater than 1. According to the invention, the performance of the interconnection circuit in the aspects of area, power consumption, speed and signal integrity is more excellent.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] Since the advent of FPGA, while its capacity has been continuously expanded, the interconnection circuit (i.e., FPGA architecture) has also gradually evolved. In the initial period of small-scale FPGAs, designers paid more attention to the design and optimization of logic units. As interconnect circuits account for an increasing share of the performance of large-scale FPGA chips, designers have begun to explore different types of interconnect circuit development. It needs to be considered that the architectural parameters are continuously increasing, forming an FPGA architecture design space with exponentially increasing capacity. Efficiently selecting an optimized architecture that satisfies design specifications from a huge architecture design space is the key to ensuring the rapid availability of FPGAs. [0003] The traditional interconnection circuit use...

AI Technical Summary

Problems solved by technology

[0003] The traditional interconnection circuit uses the transmission gate as the selector of the MUX, and its area is relatively large, which makes the chip area of ​​the entire FPGA relatively large.

In addition, even if the MOS single-tube design is adopted, the power consumption of the interconnection circuit is still limited.

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