Chip architecture and signal integrity test method

Abstract

The invention discloses a chip architecture and a signal integrity test method.The chip architecture comprises a plurality of modules to be tested and a test module, the test module comprises a function register, a data register and a state register, and when the test module receives a test instruction of a communication link of any one module to be tested, the function register is connected with the data register; and configuring the function register and the data register corresponding to the test instruction according to the test instruction, so that the state register and / or the pin of the to-be-tested module output a test result. The chip does not need to be installed on a mainboard, the signal test result of the communication link of each to-be-tested module can be obtained directly according to the test module in the chip architecture, the process is simple and rapid, the test cost is low, the test range is clear, the test effects of different to-be-tested modules can be accurately and rapidly determined, and the test efficiency is improved. And the signal integrity of the chip is ensured.

Description

technical field [0001] The invention relates to the field of chip testing, in particular to a chip architecture and a signal integrity testing method. Background technique [0002] At present, chip testing usually includes wafer wafer testing and FT (Final Test) after chip packaging, including current testing, voltage testing, functional testing, timing testing, etc., while signal integrity testing is different from wafer testing. Test and FT test, generally after the chip is installed on the main board, the whole link is tested during the operation of the chip. This test method relies on the mutual support between the motherboard and the chip, but since the range of the communication link obviously extends beyond the scope of the original chip, even if there is a problem with the communication link, it is impossible to determine whether the problem of the link is caused by the signal integrity of the chip. Due to the nature of the chip, it is impossible to check whether th...

AI Technical Summary

Problems solved by technology

This test method relies on the mutual support between the motherboard and the chip, but since the range of the communication link obviously extends beyond the scope of the original chip, even if there is a problem with the communication link, it is impossible to determine whether the problem of the link is caused by the signal integrity of the chip. It is impossible to check whether there is a problem inside the chip, and it is impossible to adjust the link on the external motherboard according to the situation of the chip.

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