Positive feedback exclusive-OR/exclusive-OR gate and hybrid logic adder

Abstract

The invention discloses a positive feedback XOR / XNOR gate and a hybrid logic adder. The hybrid logic adder comprises a positive feedback XOR / XNOR gate and an output circuit. The positive feedback exclusive-OR / XNOR gate comprises a first PMOS tube and a second PMOS tube which are used as transmission tubes, and a first NMOS tube and a second NMOS tube which form a pull-down network. The third PMOStube, the third NMOS tube and the fourth NMOS tube form a positive feedback loop; when the exclusive-OR logic output end of the positive feedback exclusive-OR / exclusive-OR gate is pulled down to be below the switching threshold value of an inverter composed of a third PMOS tube and a fourth NMOS tube, the exclusive-OR logic output end of the positive feedback exclusive-OR / exclusive-OR gate is switched off. The positive feedback loop starts to work, so that the exclusive-OR logic output end of the positive feedback exclusive-OR / XNOR gate enters an accelerated pull-down period and is successfully pulled down to a low level, and threshold-voltage-loss-free is realized; the invention has the advantages of no threshold voltage loss, and small time delay and power consumption time delay product.

Description

technical field [0001] The invention relates to an XOR / XOR gate, in particular to a positive feedback XOR / XOR gate and a mixed logic adder. Background technique [0002] VLSI needs to solve power supply problems with low power consumption and speed up operation with low latency. In logic circuits such as comparators and parity checkers, adders are widely used as basic blocks. The standard static CMOS adder is composed of 28 transistors, which is robust to voltage and transistor size changes, but because each input terminal is connected to at least one PMOS transistor and one NMOS transistor, the input capacitance increases and the power consumption delays. The time product (Power-delay Product, PDP) increases accordingly. On this basis, the improved complementary CMOS adder uses the self-dual characteristics of summation and carry to effectively reduce the area and delay, but it also requires 28 transistors and consumes too much power. Complementary Pass Transistor Logic ...

AI Technical Summary

Problems solved by technology

Although the 4T transfer transistor XOR gate can use a very small number of transistors to realize basic functions, but in the case of input signal B=0 and input signal A=VDD→0, the XOR node has a threshold voltage loss V m , so the delay and power consumption delay product of the adder realized by using the 4T transmission tube XOR gate will increase

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