Clock frequency error injection attack resisting defense circuit of security chip

Abstract

The invention discloses a clock frequency error injection attack resisting defense circuit of a security chip. The defense circuit is characterized by comprising a detection module and a judgment module; the detection module comprises a first NMOS transistor M1, a second NMOS transistor M2, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3 and a fourth transmission gate TG4, and the judgment module comprises a first Schmitt trigger A1, a second Schmitt trigger A2, a first D trigger D1, a second D trigger D2 and an XNOR gate XNOR. By means of the defense circuit, the clock frequency can be limited within a security frequency range, and thus clock frequency error injection attacks can be effectively prevented.

Description

technical field [0001] The invention relates to the field of hardware information security, in particular to a security chip defense circuit against clock frequency error injection attack. Background technique [0002] In the field of information security applications, security chips based on specific cryptographic algorithms can provide confidentiality and integrity protection for sensitive information. At the same time, the important role of security chips in information security protection makes them vulnerable to various attacks and is facing more and more serious security challenges. These attacks mainly include: static attack and dynamic attack, the former includes invasive attack and semi-invasive attack, such as micro-probe attack technology, laser scanning technology; the latter includes non-intrusive attack, such as power analysis, software attack and error Injection attack method. For the method of dynamic attack, anti-attack measures are proposed in four aspect...

AI Technical Summary

Problems solved by technology

[0005] Currently commonly used clock frequency detection circuits are relatively complex, requiring reference clocks, frequency dividers, counters, comparators, etc., and some logic operations are cumbersome, resulting in large power consumption and large chip area, and are not suitable for low-power security chips.

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