147 results about "Boolean function" patented technology

An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.

Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. Under another embodiment of the invention, the control electrode is arranged in relation to the nanotube channel element to form said conductive channel by causing electromechanical deflection of said nanotube channel element. Under another embodiment of the invention, the output node includes an isolation structure disposed in relation to the nanotube channel element so that channel formation is substantially invariant from the state of the output node. Under another embodiment of the invention, the isolation structure includes electrodes disposed on opposite sides of the nanotube channel element and said electrodes produce substantially the same electric field. Under another embodiment of the invention, a Boolean logic circuit includes at least one input terminal and an output terminal, and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. The Boolean function transformation includes a Boolean inversion within the function, such as a NOT or NOR function.

A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column. The activation unit activates at least two cells in a column of the memory array at the same time thereby to generate multiple Boolean function outputs of the data and of complementary data of the at least two cells on the first bit line and different multiple Boolean function outputs of the data and of the complementary data on the second bit line. The multiple column decoder at least activates the first and second bit lines of multiple selected columns for reading or writing. The multiple column decoder also includes a write unit to write the output of the first bit line, the second bit line or both bit lines of the selected columns into the memory array.

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate / mask and add operation in a three input arithmetic unit.

Some embodiments provide a method for locking in a mathematical relationship between a set of at least two parameters in a computer program. The method selects a first parameter. The method defines a mathematical relationship that ties the value of the first parameter to the value of a second parameter. In some embodiments, the mathematical relationship can be a mathematical function, a Boolean function, or a lookup table. The relationship could be directly entered by the user, or the computer program itself could derive it from the user's actions. In some embodiments, the first parameter can be locked to the mathematical relationship. The lock prevents the value of that parameter from being changed, except by changing the value of the second parameter. Some embodiments implement this method by using a GUI with an intuitive set of controls.

A semiconductor integrated circuit having a reverse engineering protection part that can be easily implemented without additional circuitry or process using a method for protecting against reverse engineering of the semiconductor integrated circuit. The semiconductor integrated circuit includes a logic gate and a reverse engineering protection part. The reverse engineering protection part alters the apparent Boolean functions of a logic gate. Further, the reverse engineering protection part includes at least one PMOS transistor and at least one NMOS transistor. The PMOS and NMOS transistors are constructed to remain in a state of constant on or off irrespective of an input signal applied to their gates. The PMOS transistors and the NMOS transistors are included in transistors forming the logic gate. The PMOS transistors and the NMOS transistors that remain in a state of constant on or off are formed by implanting ions into their gate channels or blocking ion implantation into their gate channels during manufacturing.

Some embodiments provide a method for locking in a mathematical relationship between a set of at least two parameters in a computer program. The method selects a first parameter. The method defines a mathematical relationship that ties the value of the first parameter to the value of a second parameter. In some embodiments, the mathematical relationship can be a mathematical function, a Boolean function, or a lookup table. The relationship could be directly entered by the user, or the computer program itself could derive it from the user's actions. In some embodiments, the first parameter can be locked to the mathematical relationship. The lock prevents the value of that parameter from being changed, except by changing the value of the second parameter. Some embodiments implement this method by using a GUI with an intuitive set of controls.

This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip.