65results about How to "Reduces off-state leakage current" patented technology

The invention discloses a three-dimensional semiconductor device comprising a plurality of memory unit transistors and a plurality of selection transistors, wherein the plurality of memory unit transistors are at least partially overlapped in the vertical direction; each selection transistor comprises a first drain electrode distributed along the vertical direction, an active region, a common source electrode formed in a substrate and a metal grid electrode distributed around the active region; each memory unit transistor comprises a channel layer distributed vertical to the surface of the substrate, wherein a plurality of interlayer insulating layers and a plurality of grid electrode stacking structures are alternately stacked along the side wall of the channel layer, and a second drain electrode is located at the top of the channel layer; the channel layer is electrically connected with the first drain electrode. According to the three-dimensional semiconductor device and a manufacturing method thereof disclosed by the invention, multi-grid MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are formed below memory unit string stacks comprising vertical channels so as to be used as the selection transistors, thus the threshold voltage control characteristic of the grid electrode is improved, the off-state leakage current is reduced, the over-etching for the substrate is avoided, and the reliability of the device is effectively improved.

The invention relates to the technical field of display processes, and particularly relates to a display device, an array substrate, a thin film transistor (TFT) and a fabricating method thereof. The thin film transistor sequentially comprises a first gate electrode, a first gate insulation layer, an active layer, a second gate insulation layer, a second gate electrode, a third gate insulation layer, a source electrode and a drain electrode, wherein source and drain light-doped regions and source and drain heavy-doped regions are respectively arranged outside regions corresponding to the active layer and the second gate electrode, the source electrode and the drain electrode are electrically connected with the source heavy-doped region and the drain heavy-doped region; the first gate electrode is arranged below the drain light-doped region of the region corresponding to the drain electrode or the first gate electrode is divided into two parts which are respectively arranged below the light-doped regions of the regions corresponding to the source electrode and the drain electrode. The invention provides the display device, the array substrate, the thin film transistor and a fabricating method thereof. The OFF leakage current of the TFT is reduced by virtue of an LDD structure; meanwhile, the effect of the ON current of the TFT is improved by virtue of a bottom gate structure, and the yield of a product is increased.

The provided manufacture method for Schottky barrier source / drain MOS transistor comprises: selecting two types of metal material to prepare asymmetric source and drain; using two metal silicatization reactions, controlling reaction time to obtain the source and drain with different height of Schottky barrier. Compared with prior art, this invention can obtain large on-off current rate or on-state current, while reduces technique complexity, and will fit to sub-50nm scale IC production.