151 results about "Ic production" patented technology

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

The invention provides a silicon wafer positioning and loading device applied to chemical mechanical polishing equipment and relates to the technical field of silicon-wafer chemical mechanical polishing equipment. A base plate of the positioning and loading device is connected to a loading guide ring on the base plate through a supporting rod; a stretching part on a lifting driving mechanism is fixedly connected to a silicon wafer fixture thereon; the silicon wafer fixture is connected to a silicon wafer guide ring outside the silicon wafer fixture; a butt-joint guiding mechanism of a silicon wafer loading device and a silicon wafer resisting-joint guiding mechanism are arranged on the loading guide ring; and an automatic displacement adjusting mechanism and an automatic resetting mechanism are arranged on the base plate or the lower part of the lifting driving mechanism. The positioning and loading device can accurately position a silicon wafer and convey the silicon wafer to a loader for processing. The positioning and loading device has the advantages of simple structure, accurate positioning, loading safety, reliable property and operation convenience, and is beneficial to realizing the automatic loading of the silicon wafer and promoting the efficiencies for positioning, loading and processing the silicon wafer. The positioning and loading device is especially suitable for the loading of the silicon wafer in the chemical mechanical polishing equipment and also can be used for loading wafers during production processes of a transistor and an integrated circuit.

An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance. The current conductors may be wire bonds, the arrangement may include a capacitor integrated in a power amplifier IC module, in which the capacitor may be provided in a separate IC from the power amplifier, the arrangement may utilise a plurality of impedance matching cells, and the wire bonds may be interdigitated across the semiconductor die. This provides the following advantages: easy to implement; increased accuracy of matching; requires few external components; easy to manufacture; no need for dedicated design flow; requires only standard IC production and test tools; uses low loss matching networks; involves only a small increase in die size (due to integration of capacitor), but the total size of the solution may be significantly reduced (e.g., by 50%) because of the reduced number of external components.

Substituted paracyclophanes are particularly useful as precursors in the formation of a cross-linkable polymer on a deposition substrate such as an electronic device being processed. The paracyclophane precursor including a cross-linkable substituent such as an alkynyl is cracked at the phenyl linkages. The substrate is subjected to the*cracked precursor. As a result, an organic polymer is formed on the substrate. Cross-linking of the polymer through reaction, e.g. thermally induced reaction, of the cross-linkable substituents produces a thermally stable cross-linked polymer. The deposition of such cross-linked polymer is particularly useful for sealing ultra low k dielectric materials used in the damascene process in the production of integrated circuits. Alternatively the polymer is also advantageous as an adhesive in wafer-to-wafer bonding. Alternatively, the polymer is useful as a hardmask to replace silicon nitride and silicon carbide in the back-end-of-the-line processing of electronic devices.

The invention discloses a positioning method for packaging and picking up chips. The method comprises steps of: using triangular unexposed regions on the edge of a wafer as positioning regions in an integrated circuit production design process; in an integrated circuit chip manufacture process, selecting one or two of the triangular unexposed regions, not exposing or etching the one or two triangular unexposed regions, and selecting a positioning point in order to achieve pickup positioning; in an integrated circuit testing flow, bypassing the triangular unexposed regions, marking good or bad chips in wafer map file, and marking untested chips as invalid chips; and in an integrated circuit chip packing and picking process, picking up chips by using a wafer map and enabling positioning marks in the wafer map to correspond to special positioning patterns on entity wafers so that one-to-one correspondence between the wafer map file and the entity wafers is achieved and a problem of erroneously picking up a chip is prevented in a packaging process.