170 results about "Ic testing" patented technology

To calibrate timing of test signals generated by all channels of an integrated circuit, each channel is programmed to generate a test signal having a repetitive pseudo-random test signal edge pattern. The test signal pattern of each channel is compared to a reference signal having the same edge pattern and the delay of each channel is adjusted to maximize cross-correlation between the test signal and the reference signal.

For testing electrical properties of packaged IC devices, there is provided an apparatus which includes a test board which is located at a testing station and provided with a plural number of contacting sockets for connecting individual IC devices to an IC tester separately and independently of each other, a loader which is located at a loading station and adapted to feed untested IC devices toward the test board, an unloader which is located at an unloading station and adapted to discharge tested IC devices from the test board at the testing station, and a device transfer mechanism which is movable across the testing station to transfer untested IC devices from the loader to the test board and also to transfer tested IC devices from the test board to the unloader. Upon detecting completion of a test on one of IC devices in one socket of the test board, a fresh untested IC device is transferred to the testing station to replace the tested IC device. As soon as the fresh IC device is set in position in that socket, execution of a test program is started with respect to that socket on the test board.

A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Resistors within the branching signal path resistively isolate the probes from one another so that a fault occurring at any one IC terminal will not affect the logic state of the test signal arriving at any other IC terminal. The isolation resistors are sized relative to signal path characteristic impedances so as to substantially minimize test signal reflections at the branch points.

We introduce a new Periodic micro coaxial transmission line (PMTL) that is capable of sustaining a TEM propagation mode up to THz band. The PMTL can be manufactured using the current photolithographic processes. This transmission line can be embedded in microscopic layers that allow many new applications. We use the PMTL to develop a wideband highly scalable connector that is then used in a Probe that can be used for connecting to microscopic scale Integrated Circuits with picoseconds High Speed Digital and near THz Analogue performance in various stages of development from R&D to production testing. These probes, in one embodiment, provide a thin pen-like vertical probe tip that matches the die pad pattern precisely that can be as agile as a high speed plotter pen, connecting on the fly to any die pattern on a wafer. This approach allows the most valuable part of the test, namely the wafer to remain stationary and safe, and the least costly part of the test, namely the probe to take most of the wear and tear. We further use the embedded PMTL to develop a modular, scaleable and fully automated Universal Test Fixture for testing chips in various stages of development mainly for digital IC chips that can be utilized in production lines with pick and place of chips on tape to test every chip before insertion into circuits. One embodiment includes a low profile wideband Signal Launcher and an alligator type RF Clip that can be used at the edge of PCB's directly for validation broads. The Signal Launcher is used to develop a new versatile Flush Top Test Fixtures for individual device testing in various stages of development from die, to packaged, to Module, to Circuit Boards. The PMTL can also provide Confined Field Interconnects (CFI) between various elements on semiconductor wafers to reduce parasitic and radiation losses and practically eliminating cross talk, thus, increasing the speed of digital IC's. The PMTL is also used to develop a Universal Test Socket, and a Hand Probe with performance up to 220 GHz.

Diagnostic tools for testing wafer-level IC devices, and a method of making the same. The first diagnostic tool can include a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between distal ends of probe members in the wafer probe and contact pads on a wafer-level IC device. A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location away from the first interface. The electrical devices are electrically coupled to the conductive traces and are configured to provide one or more of continuity testing or functionality of the wafer-level IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a dedicated IC testing device. A plurality of electrical devices are printed on the second compliant printed circuit and electrically coupled to the dedicated IC device.

A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Resistors within the branching signal path resistively isolate the probes from one another so that a fault occurring at any one IC terminal will not affect the logic state of the test signal arriving at any other IC terminal. The isolation resistors are sized relative to signal path characteristic impedances so as to substantially minimize test signal reflections at the branch points.

System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.

An integrated circuit (IC) tester includes a set of power modules mounted in a test head, each contacting a device interface board (DIB). The DIB provides power paths for delivering an output current generate by each power module to a power input terminals of one or more IC devices under test (DUTs). Power modules that supply current to the same set of DUTs communicate with one another though conductive paths provided by the DIB to ensure that all power modules begin supplying load current to that set of DUTs at the same time and to ensure that all power modules supply substantially the same amount of load current to those DUTs.

A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and / or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed.

The test system provides an array of test probes having a cross beam. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. The probes are biased upwardly through the retainer by an elastomeric block having a similar array of slots. The elastomer is then capped at its bottom by a second or lower retainer with like slots to form a sandwich with the elastomer therebetween. The bottom ends of the probes are group by probe height. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and take continue the circuits to a probe card where test signals originate.

The invention discloses an automatic IC testing and sorting device. The device comprises a feeding device, a testing device and a sorting and storing device which are arranged on a machine frame; andthe machine frame comprises a first mounting plate and a second mounting plate, wherein the first mounting plate is vertically arranged, and the second mounting plate is connected with the bottom of the first mounting plate and is obliquely arranged. An IC material tube is clamped on the feeding device, IC chips which are not tested in the IC material tube are supplied to the testing device for testing through the feeding device, after the testing is finished, the chips are classified through the sorting and storing device and are stored in a plurality of empty material tubes. According to thedevice, a clamping mechanism with the IC material tube clamped is turned over, so that the IC material tube is changed into a vertical state, and the IC chips in the IC material tube slide out and get to a vertical material channel; the IC chips can be controlled by a blocking and pressing mechanism to be fed to the testing device one by one, testing chucks clamp the IC chips and push the IC chips to a testing PCB for testing, the IC chips are received through a material receiving table after the test is completed and are classified and placed to a first material storing mechanism or a second material storing mechanism, so that the speed of sorting and storing is increased, and the labor cost is saved.

An IC tester which is capable of reducing the time required before completion of testing on all of ICs to be tested is provided. The depth (length in the Y-axis direction) of the constant temperature chamber 4 and the exit chamber 5 is expanded by a dimension corresponding approximately to one transverse width (length of the minor edge) of the rectangular test tray 3, and two generally parallel test tray transport paths or alternatively a widened test tray transport path broad enough to transport two test trays simultaneously with the two test trays juxtaposed in a direction transverse to the widened test tray transport path are provided in the section of test tray transport path extending from the soak chamber 41 in the constant temperature chamber 4 through the testing section 42 in the constant temperature chamber 4 to the exit chamber 5 so that two test trays may be simultaneously transported along the two test tray transport paths or the widened test tray transport path.

Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In one embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least one selectable capacitor is provided for each IC circuit element, such as a logic network, whose operational characteristic(s) is predicted to be and is actually identified as sub-optimal through IC testing, particularly following a process change, a mask shrink, operation of the IC at higher clock frequency, or the like. Expensive redesign is avoided by selectively coupling capacitors into the IC circuit element as needed, under control of selector logic that is responsive to control signals. Methods of operation, as well as application of the apparatus to an electronic assembly and an electronic system, are also described.

Resistances of signal paths within a interconnect structure for linking input / output (I / O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I / O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I / O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I / O ports or link the I / O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I / O ports. Existing comparators within the tester normally used to monitor the state of an IC's digital output signals are employed to measure voltage drops between the I / O ports, thereby to provide data from which resistance of signal paths within the interconnect structure may be computed.

A LSI includes a logic circuit, a PLL circuit and a built-in self-test (BIST) circuit. When the PLL circuit detects a phase lock of the system clock signal of the LSI with a reference clock signal under the condition of presence of a test instruction signal, the PLL delivers a test enable signal to the BIST circuit. The BIST circuit responds to the test enable signal to test the logic circuit in a functional test. The BIST circuit transmits the test result data to an IC tester after the functional test. Throughput of the functional test can be improved by eliminating transmission of the test enable signal from the IC tester to the LSI.