77 results about "Bicmos integrated circuits" patented technology

A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input / output (I / O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I / O pad from positive-voltage ESD events.

Trench-generated device structures fabricated using a semiconductor-on-insulator (SOI) wafer, design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, as well as methods for fabricating trench-generated device structures. The device structure includes a trench extending through the semiconductor and insulator layers of the SOI wafer and into the underlying semiconductor substrate, and a first doped region in the semiconductor substrate. The doped region, which extends about the trench, has a second conductivity type opposite to the first conductivity type. The device structure further includes a first contact extending from the top surface through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region, and a second contact extending from the top surface through the semiconductor and insulator layers to the doped region in the semiconductor substrate.

The invention discloses a crystal plane-based tri-polycrystal-plane Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a preparation method of the device. The preparation process is as follows: preparing an SOI (Silicon On Insulator) substrate; growing N type Si epitaxy and preparing a deep-trench isolator so as to form a collector electrode contact region and a nitride side wall, etching a window in a base region, growing a SiGe base region, conducting photoetching on a collector electrode window, depositing N type Poly-Si, and preparing an emitting electrode and the collector electrode to form an HBT (Heterojunction Bipolar Transistor) device; etching a deep trench in an NMOS (N-Channel Metal Oxide Semiconductor) device region, selectively growing a strain Si epitaxial layer with a crystal plane (100) to prepare an NMOS device with a Si channel; selectively growing a strain SiGe epitaxial layer with a crystal plane (110) to prepare a PMOS (P-Channel Metal Oxide Semiconductor) device with a SiGe channel, and thus forming the crystal plane-based tri-polycrystal-plane Bin CMOS integrated device and a circuit. According to the crystal plane-based tri-polycrystal-plane Bi CMOS integrated device and the preparation method, the characteristics that the electronic mobility of tensile strain Si material is higher than that of Si material, the electronic mobility of strain SiGe material is higher than of that of body Si material, and the electronic mobility is anisotropic are utilized, and based on the SOI substrate, the plane Bi CMOS integrated circuit is prepared, and the performance of the Bi CMOS integrated device is enhanced.