Three-polycrystalline SiGe HBT (Heterojunction Bipolar Transistor)-based hybrid crystal face strain BiCOMS integrated device and preparation method thereof
A technology of mixed crystal planes and integrated devices, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., and can solve problems such as confinement and low carrier material mobility of Si materials
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Embodiment 1
[0134] Embodiment 1: Preparation of 22nm mixed crystal plane BiCMOS integrated device and circuit based on three-polycrystalline SiGe HBT, the specific steps are as follows:
[0135] Step 1, SOI substrate material preparation.
[0136] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the upper substrate material, and hydrogen is injected into the substrate material;
[0137] (1b) Select the N-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on its surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;
[0138] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0139] (1d) Put the oxide layer on the surface o...
Embodiment 2
[0208] Embodiment 2: Preparation of 30nm mixed crystal plane strained BiCMOS integrated device and circuit based on three-polycrystalline SiGe HBT, the specific steps are as follows:
[0209] Step 1, SOI substrate material preparation.
[0210] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0211] (1b) Select the N-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;
[0212] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0213] (1d) Put the oxide layer on...
Embodiment 3
[0282] Embodiment 3: Preparation of 45nm mixed crystal plane strained BiCMOS integrated device and circuit based on three-polycrystalline SiGe HBT, the specific steps are as follows:
[0283] Step 1, SOI substrate material preparation.
[0284] (1a) Select the N-type doping concentration as 5×10 15 cm -3 Si wafers with a crystal plane of (100) are oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0285] (1b) Select the N-type doping concentration as 5×10 15 cm -3 The Si wafer, the crystal plane is (110), the surface is oxidized, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower active layer;
[0286] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0287] (1d) Put the oxide layer on the ...
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