Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit
A manufacturing process and process technology, applied in the field of 0.8 micron silicon bipolar complementary metal oxide semiconductor integrated circuit manufacturing process, can solve the problems of high cost and complex process flow, and achieve the effect of high resistance and high gain
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[0024] The technical solution of the present invention will be further described below in conjunction with the embodiments.
[0025] The flow process of manufacturing process of the present invention is as follows, with reference to figure 1 , the main features of which are that DP wells are also formed in N wells; the gate oxide layers of high-voltage devices and low-voltage devices are completed in the same oxidation step; and isolation NMOS devices and Bipolar NPN devices are formed on N wells with DP wells.
[0026] Such as figure 1 As shown, the process includes the following steps:
[0027] S11. Forming an N well and a P well on a P-type substrate by using ion implantation and a thermal push process. In this embodiment, the step of making the double wells specifically includes: initial oxygen; using photoresist to locate the N well region and the P well; N well ion implantation; P well ion implantation; double well advance. The above steps refer to figure 2 , these ...
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