31results about How to "Improve leakage performance" patented technology

The present invention relates to a non-fullerene acceptor compound containing benzoselenadiazole and an organic photoelectric element comprising the same. The non-fullerene acceptor compound containing benzoselenadiazole has a structure as shown in the following formula shown in the description, wherein Ar1 is a penta-heterocycles; Ar2 is a monocyclic or polycyclic aromatic heterocyclic derivative of C5-C20; pi is a C5-C20 monocyclic or polycyclic aromatic heterocyclic derivative, and m is equal to 0-5; and EG is a monocyclic or polycyclic derivative containing ketones and electron withdrawing groups. The organic photoelectric element, such as OPD or OPV, containing the benzoselenadiazole-containing non-fullerene acceptor compound can provide better light absorption wavelength range and photoelectric conversion efficiency during use.

The present invention provides an electrostatic protection structure of an image sensor and an image sensor, the image sensor comprises: a substrate including a plurality of pixel regions; a first metal interconnection layer arranged on one side of the substrate, including a pixel peripheral circuit; and a second metal layer arranged on the other side of the substrate. The electrostatic protectionstructure comprises: a first electrostatic discharge protection circuit arranged on the first metal interconnection layer and a second electrostatic discharge protection circuit arranged on the second metal layer; wherein the impedance of the second electrostatic discharge protection circuit is smaller than that of the first electrostatic discharge protection circuit, and the second electrostaticdischarge protection circuit and the first electrostatic discharge protection circuit have at least one access point. The electrostatic protection structure can reduce the resistance of a leakage path and improve the electrostatic discharge performance of a chip under the premise of not increasing the chip area.

The invention provides a high-temperature heat treatment device under a magnetic field and a method thereof for preparing a bismuth ferrite film. The device comprises a tube type heating furnace, wherein the tube type heating furnace is arranged between magnet pole heads of a direct current water-cooling magnet, the direct current water-cooling magnet is connected with a direct-current magnet power supply and a circulating water-cooling system, the heating cavity of the tube type heating furnace is communicated with a vacuumizing system and an atmosphere control system; the tube type heating furnace is also connected with a temperature controller; the water-cooling cavity is formed by adopting a double-layer nonmagnetic stainless steel material by the shell of the tube type heating furnace; heating bodies are connected in series by four silicon carbide rods; a high-temperature resistant aluminum oxide heat insulating fiber material is used as a heat insulating material; and a high-temperature aluminum oxide ceramic tube or a quartz glass tube is used as a furnace tube. The device has the characteristics of small volume, high magnetic field utilization ratio and heating efficiency,and the like, can be used for carrying out the synthesis and the heat treatment on materials below 2 Tesla of the magnetic field and under the condition of vacuum or atmosphere. The microstructure and the properties of the bismuth ferrite film prepared by the device are improved.

The invention provides a semiconductor device forming method, which comprises the steps that: a substrate, a grid structure positioned on the substrate and side walls positioned at two sides of the grid structure are provided; an auxiliary side wall is formed on the surface of the side walls; a metal layer is formed on the surface of the auxiliary side wall and the exposed substrate; and the metal layer is subjected to annealing, metal silicide is formed in the substrate, the auxiliary side wall is used for preventing the metal layer from transversely diffusing into the side walls, and the formation of the metal silicide on the side walls is avoided. The semiconductor device forming method has the advantages that the auxiliary side wall is formed on the side walls, the gap of the metal silicide in the substrate positioned at two sides of the grid structure is enlarged, the electric leakage performance in an enhancement channel of the metal silicide formed through the metal diffusion is avoided, and the electric connection of a source / drain region and a grid electrode is further avoided, so the performance of a semiconductor device is improved.

The invention provides a method for forming a semiconductor device, comprising the following steps: providing a substrate, a grid structure positioned on the substrate and a source area and a drain area which are both positioned in two side substrates of the grid structure; forming a nickel alloy layer on the exposed substrate surface containing nickel and at least one of other metals and having the thickness of 150-400 angstrom; and annealing the nickel alloy layer to form a nickel silicide in the substrate. According to the method, the diffusing capacity of the subsequently-formed nickel silicide in platinum is improved through improving the thickness of the nickel alloy layer which is in the range of 150-400 angstrom to enhance the diffusion barrier performance of the platinum element to the nickel element, thereby avoiding the diffusion of nickel to channel regions below a gate oxidation layer, reducing the generation of NiSi2 layers and improving the problem of deteriorating the electric leakage performance due to the development of the NiSi2 layer to channels.

The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a porous ultra-low dielectric constant film material and a preparation method thereof. The preparation process of the present invention adopts a sol-gel process, using organosiloxane as a precursor, by controlling the ratio of the precursor, pore-forming agent, catalyst and solvent, the concentration of the solution, and conditions such as synthesis, post-treatment and annealing temperature , prepared an ultra-low dielectric constant porous thin film material. The process is simple, the prepared film contains ordered nanopores, the surface of the film is uniform, the roughness is low, and the thermal stability is good, the dielectric constant is 1.9-2.0, and the leakage current density is 10-8 at 1MV / cm ~10-9A / cm2 order of magnitude.

The invention provides a power device structure with ESD and a preparation method thereof. The device includes an N-type substrate, an N-type epitaxial layer, a first groove, a second groove, a P-type body region, a P-type active region, an N-type active region, a dielectric layer and a metal electrode, the first groove and the The second trenches are distributed at intervals in the N-type epitaxial layer. The first trench includes a gate oxide layer and a polysilicon ESD, and a P-type doped region is formed in the polysilicon ESD; the second trench includes a gate oxide layer and a polysilicon gate. The P-type body region is located in the N-type epitaxial layer between the trenches; the dielectric layer covers the first trench, the second trench and the P-type body region; the hole lead-out region is located in the dielectric layer and is connected to the polysilicon ESD The P-type doping region, the P-type active region, and the N-type active region in the P-type body region between the first trench and the second trench are in electrical contact; the metal electrode is located on the dielectric layer. The invention can effectively reduce the area of ​​the ESD structure, is beneficial to process planarization and reduces device manufacturing cost, and helps to improve ESD leakage performance.

The invention provides a manufacturing method of an array substrate, an array substrate and a display device. The manufacturing method of the array substrate includes the step of arranging a grid metal layer on the substrate and the step of arranging a source drain metal layer on the substrate, the grid metal layer comprises a grid electrode of a thin film transistor and a first pole plate of a storage capacitor, and the source drain metal layer comprises a source electrode and a drain electrode of the thin film transistor and a second pole plate of the storage capacitor; between the step of arranging the grid metal layer and the step of arranging the source drain metal layer, the manufacturing method of the array substrate further includes the steps that at least one non-channel contact interface grid insulating layer is arranged on the substrate, the part, corresponding to the grid electrode and / or the first pole plate, of the non-channel contact interface grid insulating layer is graphed and wholly or partially thinned; a channel contact interface grid insulating layer which is not graphed is arranged on the substrate, and a channel layer of the thin film transistor is arranged on the channel contact interface grid insulating layer. The electrical properties and the storage capacitance of the thin film transistor are improved, and stray capacitance is reduced.

The present invention relates to dielectric films and methods for their preparation. The preparation method includes using the interface charge accumulation model of the first material and the second material to obtain the thickness ratio of the first material and the second material and the leakage current of the interface between the first material and the second material charge areal density; preparing a dielectric film formed of said first material and said second material of said thickness ratio. Compared with the original film, the dielectric film of the present invention effectively improves its leakage performance, reduces energy loss and increases breakdown electric field, thereby improving energy storage characteristics.