119results about How to "Extended test time" patented technology

One embodiment of the invention provides a method for providing defect information from an integrated memory chip having dynamic memory cells arranged on word lines and bit lines, wherein a word line group having a number of word lines may be replaced by a redundant word line group and wherein a bit line may be replaced by a redundant bit line to replace defective memory cells, wherein test data are written to the memory cells of the memory chip for the purpose of testing the memory cells, the written data being read out and compared with the previously written test data to generate first defect information items depending on the result of the comparison, the first defect information item indicating a defect if the written test data and the read-out data are different, the memory cells along one of the bit lines being read successively, the first defect information item in each case being generated for each of the read memory cells, the first defect information items being buffer-stored during the testing of the memory cells on the word line group, a second defect information item being generated, the second defect information item indicating a defect if at least one of the first defect information items indicates a defect, the second defect information item being output after the end of the read-out of the memory cells of the word line group along the bit line.