58 results about "Principal clock" patented technology

The invention relates to an EPA industrial bus and time sensitive network adaptation system and method, solves the technical problem that an EPA Ethernet cannot be connected with a time sensitive network in real time to construct a fast channel, and comprises an EPA endpoint device and a TSN endpoint device. The EPA endpoint device is in communication connection with a TSN bridging device througha TSN adapter, and the TSN bridging device is connected with the TSN endpoint device; the TSN adapter receives the time data issued by the main clock from the TSN bridging device, and adds a timestampin the process of receiving or transmitting the clock synchronization data to complete clock synchronization; and the TSN bridging device is used for providing time synchronization, low delay, low jitter and flow bandwidth guarantee, so that the problem is better solved, and the method can be applied to the EPA industrial technology.

A method for reducing current consumption of a mobile terminal is provided. The method includes setting a task as an initial idle task of the mobile terminal for performing a simple infinite loop in a state where all of the effective tasks performed by a program of the mobile terminal are blocked, counting global variable values of the idle task for a predetermined time according to a timer interrupt signal generated by the timer at regular intervals and storing the global variable values of the idle task as a reference value of an idle task of a program of the mobile terminal, resetting the counted value, measuring by counting the global variable values of the idle task where an effective task occupies the idle task for a predetermined time and storing the global variable values of the idle task as an idle value of the effective task according to a timer interrupt generated every predetermined time by the timer when the program of the mobile terminal performs the effective task, dividing the measured idle value of the effective task by the reference value of the idle task, to thus calculate a program idle rate of the mobile terminal, and storing the program idle rate, and changing a PLL value according to the program idle rate of the mobile terminal and varying a main clock frequency of a CPU of the mobile communication terminal.

The invention provides a method for precisely synchronizing wireless data of electroencephalogram device. The electroencephalogram device comprises a central processing system and at least one acquisition subsystem. A principal clock of the central processing system completes synchronous timing among secondary clocks of the acquisition subsystems through a method of performing multiple times of time synchronization. Each time of time synchronization comprises the steps that the central processing system sends synchronization data wirelessly to the secondary clocks of all acquisition subsystems through a first communication protocol; the acquisition subsystem resets a timestamp of the corresponding acquisition secondary clocks after receiving the synchronization data; the synchronized secondary clocks add the timestamp to each data packet and send the timestamp to the central processing system through a second communication protocol along with data information; and the central processing system performs data alignment and processing by combining the received data information according to actual requirements. The first communication protocol is a connectionless communication protocol, and the second communication protocol is a connection-oriented communication protocol.

The invention provides a chip clock circuit and a control method thereof. The chip clock circuit comprises a plurality of clocks, a clock switching module and a control module, the clocks comprise a logic OR module, a clock generation module and a trigger module, clock clk signals generated by the clocks are obtained through the input end of the clock switching module, and one clock is selected asa main clock to be output; and the control module monitors the state of each clock and controls the closing or opening of each clock. The state of a chip clock signal is monitored in real time through the control module; according to the real-time monitoring result, the clock signals are switched in time, high reliability of the clock signals of the chip is ensured, the chip is in a stable and reliable working state, the chip system can be ensured to run at a low power consumption level through a computer readable storage program, one more clock signal can be provided for the system selectively, and the flexibility of the clock of the chip system is improved.

The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.

The invention discloses a message expansion circuit of a secure hash algorithm. The message expansion circuit comprises 64 stages of pipeline circuits, and each stage of pipeline circuit comprises 16groups of latches and a combinational logic circuit; the combinational logic circuit comprises four selectors, two shift XOR circuits and an adder. Each stage of pipeline circuit comprises a main clock; 16 groups of frequency division clocks with the phase difference of 1 in sequence are also generated, the 16 groups of frequency division clocks are respectively used as trigger clocks of 16 groupsof latches, and the clock frequency of the frequency division clocks is 1 / 16 of that of the main clock, i.e., the frequency division clocks respectively trigger the corresponding latches at the moments of 0-15 of the main clock; and the clock phase difference of the same group of latches in two adjacent stages of pipeline circuits is kept at 15. According to the message expansion circuit of the secure hash algorithm, the clock and flip rate of a sequential logic circuit are reduced to 1 / 16 of those of a traditional implementation, and the power consumption of the SHA256 message expansion circuit can be greatly reduced.

A clock self-inspection circuit based on an AD8310 wave detector belongs to the technical field of navigation. The invention integrates a primary power divider, a secondary power divider, an AD8310 detector, a voltage comparator, a linear voltage regulator, and a clock generator in one design; realizes the switching function of the main clock signal and the standby clock signal; adopts a The method of using the first-stage power divider and the second-level power divider in series improves the isolation between the main clock signal and the standby clock signal, and avoids the problem that the standby clock signal cannot be turned on due to the wrong interpretation of the voltage comparator when the main clock signal is turned off. The clock self-inspection circuit proposed by the present invention converts the power of the main clock signal into a voltage value by using a logarithmic detector, judges the on-off of the main clock signal, and passes the voltage comparator to realize the control of the enable signal of the linear voltage regulator , can accurately self-test the main clock signal. The invention has high reliability, light weight, low power consumption and strong practical value.

The invention discloses a camera control method, device, electronic device and medium of a terminal. The terminal pre-stores a first code whose main clock driving current for driving the camera is the first current and the main clock driving current used for driving the camera is the first current. The second code of two currents, the first current is smaller than the second current, and the method includes: using the first code to drive the main clock driving current of the camera to be the first current; after the camera of the terminal obtains the starting frame image, detecting the starting frame image Whether the frame image is an abnormal image; if the initial frame image is an abnormal image, the main clock driving current that uses the second code to drive the camera is switched to the second current. The method, device, electronic device and medium provided by the present invention are used to solve the technical problem in the prior art that the battery life of the mobile phone and the shooting quality of the camera cannot be taken into account, and the technical effect of taking into account the battery life of the mobile phone and the shooting quality of the camera is achieved.

The invention discloses a multiphase clock generation circuit with random disturbance added, the clock generation circuit includes a main clock module, a random signal generation module and a buffer matrix switch module; the main clock module is used to generate N multiphase clock signals; The buffer matrix switch module is used to randomly switch the input transmission paths of the N multi-phase clock signals under the control of the random control signal output by the random signal generation module, and output N multi-phase clock signals with random disturbance added. clock signal. The present invention whitens the clock phase error by adding random disturbance, and only loses a small amount of signal-to-noise ratio, which can eliminate the influence of multi-phase clock phase error on the performance of high-precision TI ADC in real time, and can track and eliminate the clock phase error as the working environment changes. The impact of changing fluctuations can whiten the error spurious components at a fixed frequency into the noise floor, without interrupting the normal operation of TI ADC, the design is simple to implement, and the stability is high.

A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseuodo-random pattern generator which provides the pseudo-random pattern.

A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs according to its own clocks, including multiple-stage totally unsynchronized clocks, in order to process a stream of instructions. The method includes the steps of generating a virtual model master clock having a clock cycle, and initializing each of the function units at the beginning of respectively corresponding processing cycles. The method further includes operating each function unit during a respectively corresponding processing cycle to carry out a task with respect to one of the instructions, in order to produce a result. Respective results are all evaluated in synchronization, by means of the master clock. This enables the instruction processing operation to be modeled using a sequential computer language, such as C or C++.