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Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU

一种指令流、指令的技术，应用在并发指令执行、具有多个处理单元的架构、机器执行装置等方向，能够解决不能CPU操作建模等问题

Inactive Publication Date: 2007-10-24
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, since the internal timing of RISC CPUs runs in a multi-stage pipeline mode, as described above, the sequential execution characteristics of compiled model languages ​​such as C or C++ cannot correctly model CPU operations, and have acceptable clock standards precision or accuracy

Method used

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  • Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU
  • Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU
  • Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU

Examples

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Embodiment Construction

[0012] Referring to FIG. 1, there is shown a superscalar RISC CPU 100 implemented as an arrangement of concurrently operating functional blocks or functional units. The functional units include an instruction reader 102 , a multiplexer / distributor 104 and an execution unit 106 . Reorder buffer 108 and completion unit input reorder buffer 110 collectively function as a completion buffer. The interaction between the functional units 102-110 in FIG. 1, together with the bus interface unit 112 and the register file 114, will be described in detail later.

[0013] Referring further to FIG. 1, there is shown a timer 116 and an instruction dispatch unit 118, connected to the multiplexer 104, for dispatching instructions. Also shown is load / store unit 124 , interconnected with instruction cache / data cache 126 , and address translation unit 128 , as well as coprocessor 130 and cache 132 . RISC CPU 100 further includes a branch processing unit 134 , an instruction reservation station ...

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Abstract

A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs according to its own clocks, including multiple-stage totally unsynchronized clocks, in order to process a stream of instructions. The method includes the steps of generating a virtual model master clock having a clock cycle, and initializing each of the function units at the beginning of respectively corresponding processing cycles. The method further includes operating each function unit during a respectively corresponding processing cycle to carry out a task with respect to one of the instructions, in order to produce a result. Respective results are all evaluated in synchronization, by means of the master clock. This enables the instruction processing operation to be modeled using a sequential computer language, such as C or C++.

Description

technical field [0001] The invention disclosed and claimed herein relates generally to a method and apparatus for modeling a super scalar central processing unit (CPU) using a specific computer language. More specifically, the invention relates to a method of the above-mentioned type, wherein the CPU operation is characterized by concurrently scheduled instruction streams, and the specific language is a sequential language, such as C or C++. More specifically, the present invention relates to a method of the above-mentioned type, wherein a plurality of concurrently operating functional units included in a CPU are respectively synchronized with a virtual model master clock or a reference clock. Background technique [0002] As known to those skilled in the art, a Reduced Instruction Set Computer (RISC) is a type of microprocessor designed to execute a reduced number of computer instructions. This enables the microprocessor to run at higher speeds. In the current superscalar...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F15/80
CPCG06F9/3869G06F9/3885
Inventor 奥利弗·克伦·班恩
Owner INT BUSINESS MASCH CORP
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