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A kind of ldpc decoder and decoding method based on fpga

A decoder and decoding technology, applied in the field of LDPC decoder and decoding, to achieve the effect of reducing hardware resource occupancy rate, avoiding use, and high throughput rate

Active Publication Date: 2022-08-09
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] The purpose of the present invention is to solve the problem of how to improve the throughput of the LDPC decoder while reducing hardware resource overhead

Method used

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  • A kind of ldpc decoder and decoding method based on fpga
  • A kind of ldpc decoder and decoding method based on fpga
  • A kind of ldpc decoder and decoding method based on fpga

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specific Embodiment approach 1

[0040] Specific implementation one: as figure 1 As shown, an FPGA-based LDPC decoder described in this embodiment, the LDPC decoder includes a channel likelihood ratio ping-pong storage module, a confidence message storage module, a hard decision information storage module, and a decoding result. Ping-pong cache module, check node update module, variable node update module, hard decision check module, control module and output module;

[0041] The channel likelihood ratio ping-pong storage module is configured to receive and store the channel log likelihood ratio information input to the decoder, and provide the channel log likelihood ratio information to the variable node update module;

[0042] The confidence message storage module is used to store the confidence message calculated by the check node update module and the variable node update module;

[0043] The check node update module is used to complete the calculation of the confidence message from the check node to the...

specific Embodiment approach 2

[0059] Embodiment 2: This embodiment is different from Embodiment 1 in that the channel likelihood ratio ping-pong storage module is a ping-pong storage pair structure.

specific Embodiment approach 3

[0060] Embodiment 3: This embodiment is different from Embodiment 2 in that the channel likelihood ratio ping-pong storage module includes 16 pairs of RAMs with a bit width of P×8 and a depth of 511 / P, where P is the confidence message storage The number of data bits per address of the module.

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Abstract

An FPGA-based LDPC decoder and a decoding method belong to the technical field of channel coding in the communication field. The invention solves the problem of how to improve the throughput rate of the LDPC decoder while reducing the hardware resource overhead. The present invention separates the serial circuit from the parallel part by using the method of ping-pong buffering, and each part adopts independent clocks to ensure the inflow and outflow of continuous data streams and high throughput; and the present invention adopts a new circular storage method to The problem of address conflict is solved, the use of the barrel shift register or the connection network is avoided, and the occupancy rate of hardware resources of the decoding circuit is reduced at the same time. When the partial parallel decoding structure of the present invention is adopted, the parallel degree is 7, the main clock frequency is 110MHz, the code rate is 7 / 8, the sub-matrix dimension is 511, the number of iterations is 15, and the average number of variable node update clocks is 1.008, the throughput rate The maximum achieved was about 356.48Mbps. The present invention can be applied to the technical field of channel coding in the communication field.

Description

technical field [0001] The invention belongs to the technical field of channel coding in the communication field, and particularly relates to an LDPC decoder and a decoding method. Background technique [0002] With the continuous progress of modern communication technology, communication systems are gradually developing towards higher throughput, larger capacity and higher reliability. Error correction codes, as a type of channel coding, are a main method to improve communication quality. Among them, the LDPC code is a block code whose performance is close to the Shannon limit, and has the characteristics of resistance to continuous burst errors, strong error correction ability, low implementation complexity, and small decoding delay. [0003] The minimum sum decoding algorithm suitable for hardware implementation has been widely used. Specify R cv Represents the confidence information transmitted from the c-th check node to the v-th variable node, L vc Represents the co...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11H04L1/00
CPCH03M13/1125H04L1/0057H04L1/0076
Inventor 张佳岩苏怡宁赵洪林马永奎卢昊高玉龙白旭
Owner HARBIN INST OF TECH
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