DLL system based on successive approximation PID control algorithm

Abstract

The invention provides a DLL system based on a successive approximation PID control algorithm. The system comprises: a phase-locked output clock rising edge detection module, a reference clock risingedge detection module, an error counting module, a successive approximation PID control module, and a variable mode frequency division module and an initialization module, furthermore, a system clockis the main clock of the entire system, a reference clock is a clock signal that needs to be locked, a phase-locked output clock is a locked clock signal, the system continuously and circularly adjusts the phase-locked output clock and finally outputs a clock signal with a fixed phase difference with the reference clock after a plurality of cycles The reference clock of the system can not only work at a high frequency band, but also can work at a low frequency band; no delay line is required, so that the area can be reduced, and the power consumption can be reduced; the problem of inconsistentdelay times of delay units is avoided; and the design complexity is low, and the design can be easily implemented on FPGA and ASIC.

Description

technical field [0001] The present invention relates to the field of delay-locked loop (Delay-Locked Loop, DLL), in particular to a DLL system based on a step-by-step proportional-integral-derivative control (proportional-integral-derivative control, PID) control algorithm. Background technique [0002] With the development of integrated circuits, clock quality has increasingly become the focus of attention. DLL (Delay-Locked Loop), that is, delay-locked loop, is widely used in the control of the internal clock of the chip, such as clock delay elimination, frequency multiplication and frequency division, and clock correction. [0003] The DLL adjusts the delay time on the delay line so that the rising edges of the DLL output clock (Dllclk) and the reference clock (Refclk) are aligned to complete the phase locking function. figure 1 It is a functional schematic diagram of the existing DLL system. In a circuit without DLL phase lock, the rising edge of the output clock (Actc...

AI Technical Summary

Problems solved by technology

First, the frequency of the reference clock (Refclk) is limited by the length of the delay line, which means that the frequency of the reference clock (Refclk) cannot be very low, otherwise the length of the delay line will become very long; too long delay line will Occupying a larger area will also cause an increase in power consumption

Moreover, in the FPGA implementation process, it is impossible to guarantee that the delay time of each delay unit after synthesis is consistent, which will make the delay time required by the phase selector uncontrollable, resulting in the actual delay time may exceed the required delay time. After a while, the system enters an out-of-lock state.

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