Methods and Systems for Generation of Balanced Secondary Clocks from Root Clock

Abstract

A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseuodo-random pattern generator which provides the pseudo-random pattern.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority from Indian Provisional Application No. 202141007690, filed Feb. 24, 2021, incorporated herein by reference in its entirety.BACKGROUND[0002]The disclosure generally relates to generation of balanced secondary clocks from a root clock.Description of the Related Art[0003]In RF communication and other mixed signal systems, analog circuitry may operate in the gigahertz (GHz) range while digital circuitry may operate at lower frequencies (e.g., 400-500 MHz) for optimal power efficiency. For example, in a radio base station, a mixer, a phase lock loop, and an up-converter may operate at 3 GHz while a serial data interface and a digital pre-distortion may operate at 500 MHz. Existing systems generally require a number of identical parallel hardware working in unison to derive secondary clocks from a root clock (also called primary clock). In one existing method, the root clock is divided using a clock divider whi...

AI Technical Summary

Benefits of technology

The patent describes a system and method for generating secondary clock signals from a primary clock signal. The system includes a dithered clock divider that divides the primary clock signal into blocks of dithered clock signals based on a random division ratio. The dithered clock signals are then used to generate the secondary clock signals through a multi-phase clock generator. The secondary clock signals include a pseudo-random pattern that indicates their edge positions. A random division ratio selector is used to select the first phase of the dithered clock signal as the primary clock signal for the system. The system can generate multiple secondary clock signals from the dithered clock signal based on the selected phase. This technology allows for the efficient and accurate generation of secondary clock signals for various applications.

Problems solved by technology

This leads to an under-utilization of clock edges because not all edges of the root clock are utilized, resulting in digital spurs in the system.

Thus, a drawback of some existing systems is that the number of parallel hardware depends on the division factor as well as the root clock frequency.

A drawback of other existing systems is that under utilization of all edges of the root clock leads to digital clock spurs which couple to analog circuitry and degrade system performance.

For example, periodic activities of digital circuitry at clock edges cause instantaneous surge in current demand which causes a change (e.g., a slight decrease or “dip”) in a supply voltage, thereby limiting common mode range of analog circuitry.

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