Clock synchronization device and method

A clock synchronization and clock technology, which is applied in the field of network communication, can solve problems such as unstable operation of the subsequent circuit system, influence of the subsequent circuit, and uncertain clock phase.

Inactive Publication Date: 2008-06-11
SHANGHAI HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The main clock module and the standby clock module of the above-mentioned prior art use different clock sources, and the initial phases of the two clock sources are different after each power-on, so the phases of the two clocks are uncertain, and the difference is relatively large , so that when the active and standby clock modules are switched over, the output clock frequency will have a phase jump, and the size of the phase jump is determined by the phase difference between the 0# and 1# output clocks
And this kind of jump will have a serious impact on the back-stage circuit of the system, and even cause the back-stage circuit system to work unstable.

Method used

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Embodiment 1

[0018] Embodiment 1. A device for clock synchronization. As can be seen from FIG. 2 , the device includes a monitoring unit 201 , a control selector 202 , a first clock unit 203 and a second clock unit 207 .

[0019] Wherein, the monitoring unit 201 is used to monitor whether the master clock fails, and the master clock may be implemented by the first clock unit 203 or the second clock unit 207 . For example, if the first clock unit 203 is used in normal operation, then the first clock unit 203 is the master clock, and the second clock unit 207 is the backup clock, and vice versa.

[0020] Wherein, the control selector 202 is used to select the standby clock as the main clock according to the result of the monitoring unit 201, and the clock provides clock input for the subsequent circuit. For example, if the first clock unit 203 serving as the master clock fails, the second clock unit 207 will be selected as the master clock. Generally, the output frequency of the first clock...

Embodiment 2

[0034] Embodiment 2, a device for clock synchronization. It can be seen from FIG. 3 that the device is similar to FIG. In the second clock unit, a second frequency division and phase modulation unit 302 is added, and a first control selector 303 is also added.

[0035] Wherein, the first frequency division and phase modulation unit 301 is used to divide the output signal of the first phase-locked loop 206, and receive the synchronization signal and the frequency division signal output by the second frequency division and phase modulation unit 302, if the second frequency division and phase modulation unit 302 is selected A clock unit 203 is used as the main clock, assuming that the frequency of the output signal of the first frequency division and phase modulation unit 301 is f13, f13 is obtained by frequency division of f12, and the phase is determined by the synchronization signal of the first frequency division and phase modulation unit 301, usually The signal obtained by f...

Embodiment 3

[0042] Embodiment 3, a method for clock synchronization, specifically comprising the following steps:

[0043] A same clock signal is selected for the first clock and the second clock, and the clock signal may be a clock signal generated by a clock source of the first clock or the second clock.

[0044] The first clock and the second clock respectively smooth the phase transitions generated by the selected clock signals, so that the output signals of the first clock and the second clock are synchronized.

[0045] Optionally, the method further includes:

[0046] The first clock or the second clock as the main clock is monitored, and when the main clock fails, the second clock or the first clock as the backup clock is selected to provide clock input for the subsequent circuit.

[0047] In addition, those of ordinary skill in the art can understand that all or part of the steps in the method of the above-mentioned embodiments can be completed by instructing related hardware thr...

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PUM

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Abstract

The invention, relating to the network service technical field, discloses a clock synchronization device and a method. The device comprises a first clock unit and a second clock unit, wherein, the first clock unit is used for choosing a clock signal and smoothing processing the phase jump generated by the chosen clock signal; the second clock unit is used for choosing the clock signal the same as the first clock unit chooses and smoothing processing the phase jump generated by the chosen clock signal to ensure that the signal outputted by the second clock unit is synchronized with the signal outputted by the first clock unit. The invention ensures that the signals outputted by the two clocks have good synchronization effect; therefore, the stability of the operation of a post-stage circuit is not affected when a principal clock and an auxiliary clock are rearranged.

Description

technical field [0001] The invention relates to the technical field of network communication, in particular to a clock synchronization device and method. Background technique [0002] In order to improve the availability of a certain functional part in the system, the method of resource redundancy is often used in the system structure to configure at least one component with the same function to complete a functional fault-tolerant strategy. When working normally, there is only one component in the system to complete the corresponding function, which is called the main component. Other parts with the same function are in standby state, called spare parts. When the main part fails, it will automatically become the backup part, and the backup part will automatically be upgraded to the main part to continue working to ensure the stable operation of the system. This is called the main-standby switching working mode. However, when the active / standby switchover occurs, the clock...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/22G06F11/16
Inventor 胡骥王显安
Owner SHANGHAI HUAWEI TECH CO LTD
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