Clock synchronization device and method

Abstract

The invention, relating to the network service technical field, discloses a clock synchronization device and a method. The device comprises a first clock unit and a second clock unit, wherein, the first clock unit is used for choosing a clock signal and smoothing processing the phase jump generated by the chosen clock signal; the second clock unit is used for choosing the clock signal the same as the first clock unit chooses and smoothing processing the phase jump generated by the chosen clock signal to ensure that the signal outputted by the second clock unit is synchronized with the signal outputted by the first clock unit. The invention ensures that the signals outputted by the two clocks have good synchronization effect; therefore, the stability of the operation of a post-stage circuit is not affected when a principal clock and an auxiliary clock are rearranged.

Description

technical field [0001] The invention relates to the technical field of network communication, in particular to a clock synchronization device and method. Background technique [0002] In order to improve the availability of a certain functional part in the system, the method of resource redundancy is often used in the system structure to configure at least one component with the same function to complete a functional fault-tolerant strategy. When working normally, there is only one component in the system to complete the corresponding function, which is called the main component. Other parts with the same function are in standby state, called spare parts. When the main part fails, it will automatically become the backup part, and the backup part will automatically be upgraded to the main part to continue working to ensure the stable operation of the system. This is called the main-standby switching working mode. However, when the active / standby switchover occurs, the clock...

AI Technical Summary

Problems solved by technology

[0005] The main clock module and the standby clock module of the above-mentioned prior art use different clock sources, and the initial phases of the two clock sources are different after each power-on, so the phases of the two clocks are uncertain, and the difference is relatively large , so that when the active and standby clock modules are switched over, the output clock frequency will have a phase jump, and the size of the phase jump is determined by the phase difference between the 0# and 1# output clocks

And this kind of jump will have a serious impact on the back-stage circuit of the system, and even cause the back-stage circuit system to work unstable.

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