Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Control circuit

A technology for controlling circuits and controlling signals, which is applied in the field of circuits and can solve problems such as the inability to achieve real-time control of clock sources

Active Publication Date: 2021-01-29
EDGELESS SEMICON CO LTD OF ZHUHAI +1
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Because the two counters need to be counted for a period of time before making a comparison, there is a period of time lag. For application scenarios with high real-time requirements of industrial control, real-time control of the clock source cannot be achieved.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Control circuit
  • Control circuit
  • Control circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0041]This embodiment includes all the content in the above embodiments, and will not be repeated here, wherein, the sampling unit 100 in this embodiment includes: the plurality of delay units and a plurality of triggers;

[0042] There are one or more delay units as initial signal input terminals in the plurality of delay units, and each of the delay units as initial signal input terminals is respectively used to receive the setting signal and connect N delay units in series, where N is a natural number;

[0043] There are a plurality of delay units serving as output terminals of the sample signal among the plurality of delay units, and different delay units output sample signals with different delay times;

[0044] The sample input end of each flip-flop is connected to a delay unit as the output end of the sample signal, wherein different flip-flops are connected to different delay units, and the clock input end of each flip-flop is connected to The main clock source is use...

Embodiment 2

[0054] This embodiment includes all the content in Embodiment 1, and will not be repeated here. In this embodiment, among multiple flip-flops, the output end of a flip-flop is connected in series with an inverter as the initial signal input end. The delay unit is connected.

[0055] In this embodiment, the phase of the output signal of the flip-flop is reversed by 180 degrees after passing through the inverter, so that the signal at the output end of the flip-flop can be converted into a transition signal and input to the delay unit, so that the sample signal can become a transition signal , in order to sample the sample signal.

[0056] Preferably, among the plurality of flip-flops, the flip-flop which takes the sample signal with the shortest delay time as the input signal is connected in series with the inverter.

[0057] In this embodiment, by connecting the sample signal with the shortest delay time as the input signal flip-flop and the inverter in series, the delay unit...

Embodiment 3

[0059] This embodiment includes all the content of Embodiment 1 and Embodiment 2, which will not be repeated here, wherein, in this embodiment, the control unit 200 includes a plurality of XOR gates and OR gate groups,

[0060] The first input ends of the plurality of XOR gates are all connected to the output end of the same flip-flop in the plurality of flip-flops, and the second input ends of the plurality of XOR gates are respectively connected to the output ends of other flip-flops, wherein , the second input ends of different XOR gates are connected to different flip-flops;

[0061] The input terminals of the OR gate group are connected to the output terminals of the plurality of exclusive OR gates, and are used to generate control signals according to the output signals of the plurality of exclusive OR gates, and transmit the control signals to the processor 300, so that the processor 300 controls the abnormal situation of the master clock source according to the control...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a control circuit. The control circuit comprises a sampling unit and a control unit, wherein the sampling unit is connected to the main clock source and used for setting a sampling period according to a clock signal output by the main clock source and sampling a group of sample signals according to the sampling period, and the control unit is connected to the sampling unitand used for generating a control signal according to a sampling result of the sampling unit and transmitting the control signal to the processor. Therefore, the processor can control the abnormal condition of the main clock source according to the control signal. According to the invention, the main clock source of the processor is used as the sampling clock of the control circuit, the sample signal is sampled according to the sampling clock, the control signal is output to the processor according to the sample result, and the processor processes the abnormal condition of the main clock source according to the control signal, so that the real-time control of the main clock source is realized.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a control circuit. Background technique [0002] At present, industrial control MCU ((Microcontroller Unit, micro control unit) generally has a control circuit. The function of the control circuit is to detect the abnormality of the MCU clock, such as glitches and irregular cycles. , to remind the running MCU so that the MCU can take corresponding measures, thereby improving the reliability of the MCU chip in various application scenarios with relatively harsh electrical environments, and effectively avoiding the abnormality of the MCU application system caused by the abnormality of the MCU clock uncontrollable. [0003] The control circuit in the prior art requires two counters, one counter uses the reference clock as the clock source, and the other counter uses the detected MCU clock as the clock source, when the difference between the count values ​​of the two counters exceeds the pre...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/042
CPCG05B19/0423G05B2219/25257
Inventor 黄俏聂玉庆
Owner EDGELESS SEMICON CO LTD OF ZHUHAI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com