A Multi-phase Clock Generation Circuit Adding Random Disturbance

Abstract

The invention discloses a multiphase clock generation circuit with random disturbance added, the clock generation circuit includes a main clock module, a random signal generation module and a buffer matrix switch module; the main clock module is used to generate N multiphase clock signals; The buffer matrix switch module is used to randomly switch the input transmission paths of the N multi-phase clock signals under the control of the random control signal output by the random signal generation module, and output N multi-phase clock signals with random disturbance added. clock signal. The present invention whitens the clock phase error by adding random disturbance, and only loses a small amount of signal-to-noise ratio, which can eliminate the influence of multi-phase clock phase error on the performance of high-precision TI ADC in real time, and can track and eliminate the clock phase error as the working environment changes. The impact of changing fluctuations can whiten the error spurious components at a fixed frequency into the noise floor, without interrupting the normal operation of TI ADC, the design is simple to implement, and the stability is high.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and relates to a clock generation circuit, more particularly, to a multiphase clock generation circuit adding random disturbance. Background technique [0002] In a time-interleaved data converter (TI ADC), the phase accuracy of the multi-phase clock directly affects the system performance, while the multi-phase clock generation circuit is often affected by factors such as process deviation and circuit mismatch, and inevitably has phase errors. In high-precision TI ADCs, the clock phase error will lead to a significant drop in the dynamic performance SFDR, which is at k f s / L±f in (f s is the TI ADC sampling frequency, f in is the input signal frequency, L is the number of integrated channels of the TI ADC, and error spurious components appear at k=1,2,...,L-1) and need to be corrected. At present, the conventional method to eliminate the clock phase error is usually to use foreground trim...

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Problems solved by technology

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a multi-phase clock generation circuit adding random disturbances, which is used to solve the current existing TI ADC clock phase error elimination technology, which has high design and implementation complexity, The problem of limited stability and reliability or the inability to track and eliminate the clock phase error in real time as the working environment changes

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