Clock delay detection method and device, clock delay compensation method and device, terminal and readable storage medium

Abstract

The embodiment of the invention provides clock delay detection and compensation methods and devices, a terminal and a readable storage medium, and the clock delay detection method comprises the steps:transmitting a first synchronous clock to a to-be-detected clock module through a first physical link; receiving a feedback clock which is transmitted by the to-be-detected clock module through a second physical link and is adjusted according to the phase of the first synchronous clock, and determining the delay of the to-be-detected clock module according to the feedback clock, the self-return clock, the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link. The invention also provides the clock delay detection and compensation methods and devices, the terminal and the readable storage medium. By calculating the delay of a main clock module and the delay caused by the physical characteristics of a first physical link and a second physical link, the error of time delay caused by detecting clock distribution of switch equipment can be further reduced, so that the precision of clock time delay detection is improved.

Description

technical field [0001] Embodiments of the present invention relate to but are not limited to the field of communication technologies, and specifically, relate to but are not limited to a clock delay detection and compensation method, device, terminal, and readable storage medium. Background technique [0002] With the continuous improvement of network throughput, there are more and more types of service cards and rack slots for large-capacity switches. The system architecture of the clock of the whole switch is usually composed of a synchronous clock network distributed by the master clock. The slave clocks of each service card receive the synchronous clock delivered by the master clock through the backplane, and synchronize its frequency and phase. Due to the different lengths of traces from the main clock to the backplane and connectors between different slots, there are different delay errors when the synchronous clock arrives at each service card. The error ranges from a...

AI Technical Summary

Problems solved by technology

Due to the different lengths of traces from the main clock to the backplane and connectors between different slots, there are different delay errors when the synchronous clock arrives at each service card. The error ranges from a few nanoseconds to hundreds of nanoseconds, resulting in different There is a delay error between the phases of the service cards between the slots and the reference phase of the main clock. This error makes the switch unusable in high-precision clock synchronization scenarios.

[0003] Existing communication equipment mainly adopts the traditional method of manually compensating the delayed phase of the synchronous clock, which uses an instrument with time and phase detection functions to measure the synchronous clock signal of the main clock module across the backplane to the service card from the clock until it is synchronized The delay time on the chip is then compensated at the start of the business in the form of a quantitative constant value. This compensation method still has errors above the nanosecond level, because under different temperature conditions and different power supply voltages, the same Even under the same temperature conditions and the same power supply voltage, due to the production process, on boards produced in different batches, due to the problem of inconsistent line width control, impedance Matching inconsistencies and other issues make it difficult to determine the real delay by manual compensation. It can only reduce the error range of tens to hundreds of nanoseconds to a few nanoseconds, and the delay error of its detection is still relatively large. It only meets the high-precision clock synchronization application scenario, but for the ultra-high-precision clock synchronization application scenario, this delay detection and compensation method still has a large error on the device, and the delay error needs to be further reduced

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