94 results about "Pipeline (computing)" patented technology

The invention discloses a convolutional neural network hardware accelerator for solidifying a full network layer on a reconfigurable platform. The accelerator comprises a control module which is usedfor coordinating and controlling an acceleration process, including the initialization and synchronization of other modules on a chip, and starting the interaction of different types of data between each calculation core and an off-chip memory; a data transmission module which comprises a memory controller and a plurality of DMAs and is used for the data interaction between each on-chip data cacheand the off-chip memory; a calculation module which comprises a plurality of calculation cores for calculation, wherein the calculation cores are in one-to-one correspondence with different network layers of the convolutional neural network; wherein each calculation core is used as one stage of an assembly line, and all the calculation cores jointly form a complete coarse-grained assembly line structure, and each calculation core internally comprises a fine-grained computing pipeline. By implementing end-to-end mapping between hierarchical computing and a hardware structure, the adaptabilitybetween software and hardware features is improved, and the utilization efficiency of computing resources is improved.

A shuffler receives information associated with partition segments of map task outputs and a pipeline policy for a job running on a computing device. The shuffler transmits to an operating system of the computing device a request to lock partition segments of the map task outputs and transmits an advisement to keep or load partition segments of map task outputs in the memory of the computing device. The shuffler creates a pipeline based on the pipeline policy, wherein the pipeline includes partition segments locked in the memory and partition segments advised to keep or load in the memory, of the computing device for the job, and the shuffler selects the partition segments locked in the memory, followed by partition segments advised to keep or load in the memory, as a preferential order of partition segments to shuffle.

The invention discloses a special circuit for a neural network and a related computing platform and implementation method thereof. The special circuit comprises: a data reading module which comprisesa feature map reading sub-module and a weight reading sub-module which are respectively used for reading feature map data and weight data from an on-chip cache to a data calculation module when a depthwise convolution operation is executed, wherein the feature map reading sub-module is also used for reading the feature map data from the on-chip cache to the data calculation module when executing pooling operation; a data calculation module which comprises a dwconv module used for executing depthwise convolution calculation and a pooling module used for executing pooling calculation; and a datawrite-back module which is used for writing a calculation result of the data calculation module back to the on-chip cache. The use of hardware resources is reduced by multiplexing the read logic andthe write-back logic of the two types of operations. The special circuit provided by the invention adopts a high-concurrency pipeline design, so that the computing performance can be further improved.

A system may include memory containing: (i) a master data set representable in columns and rows, and (ii) a query expression. The system may include a software application configured to apply a machine learning (ML) pipeline to an input data set. The system may include a computing device configured to: obtain the master data set and the query expression; apply the query expression to the master data set to generate a test data set, where applying the query expression comprises, based on content of the query expression, generating the test data set to have one or more columns or one or more rows fewer than the master data set; apply the ML pipeline to the test data set, where applying the ML pipeline results in either generation of a test ML model from the test data set or indication of an error in the test data set; and delete the test data set from the memory.

The invention provides a memory resource static deployment system, comprising a memory resource obtaining component which is used for obtaining the memory resource quantity of each computing device, alife cycle acquisition component which is used for acquiring the life cycle of each logic output cache of each task node from the start of written data to the overwriting of the data on the basis ofall topological paths to which each task node of the task relationship topological graph to be deployed on the plurality of computing devices belongs, a minimum data pipeline interval searching component which is used for searching a minimum data pipeline interval suitable for the system between 0 and the maximum floating point operation value, and a memory pool number allocation component which is used for rounding up the quotient obtained by dividing the acquired life cycle of each logic output cache by the minimum data flow interval to obtain an integer so as to allocate the memory pools ofthe integer parts to the corresponding logic output caches.

In accordance with various embodiments, described herein is a system (Data Artificial Intelligence system, Data AI system), for use with a data integration or other computing environment, that leverages machine learning (ML, DataFlow Machine Learning, DFML), for use in managing a flow of data (dataflow, DF), and building complex dataflow software applications (dataflow applications, pipelines). Inaccordance with an embodiment, the system can provide data governance functionality such as, for example, provenance (where a particular data came from), lineage (how the data was acquired/processed), security (who was responsible for the data), classification (what is the data about), impact (how impactful is the data to a business), retention (how long should the data live), and validity (whether the data should be excluded/included for analysis/processing), for each slice of data pertinent to a particular snapshot in time; which can then be used in making lifecycle decisions and dataflow recommendations.

The invention discloses a reconfigurable processor and a configuration method. The reconfigurable processor comprises a reconfigurable configuration unit and a reconfigurable array; the reconfigurable configuration unit is used for providing reconfiguration information for reconfiguring a computing structure in the reconfigurable array according to an algorithm matched with the current application scene; the reconfigurable array comprises at least two stages of computing arrays, and the reconfigurable array is used for connecting the two adjacent stages of computing arrays into a data path pipeline structure meeting the computing requirements of an algorithm according to the reconfiguration information provided by the reconfigurable configuration unit; and in the same level of computing array, the pipeline depths of different computing modules accessed to the data path pipeline structure are equal, so that the different computing modules accessed to the data path pipeline structure synchronously output data. Therefore, the reconfigurable processor can configure adaptive assembly line depth according to different algorithms, and on this basis, the overall streamline of the data processing operation of the reconfigurable array is realized, and the data throughput rate of the reconfigurable processor is improved.

The invention relates to a technical field of integrate circuit design, specifically to a two-dimension parity check error detecting method in an advanced encryption standard and an implement hardware thereof. The method, by performing a two-dimension parity check in a horizontal direction and a vertical orientation for the data in the advanced encryption standard, can completely covers the odd number errors by performing a two-dimension parity check in a horizontal direction and a vertical orientation for the data in the advanced encryption standard, has a skyhigh percentage of coverage for the even number errors, especially completely covers the two errors in the condition the number of the error is two, and is capable of effectively resisting error impact. The hardware for actualizing the invention uses a completely parallel construction between a principal operation module and a two-dimension parity check digit computation module, wherein, in the principal operation module, 128 bit data are divided into 4 groups of 32 bit data and uses 2-degree pipeline architecture, and the parity check digit computation module uses a 32 bit data computing mode. The hardware structure has no affect on the data throughput in the in an advanced encryption standard, the leading in extra hardware has a low cost, and the invention is fit for an application area with a high security requirement and a strict hardware area requirement.

Aspects of the disclosure relate to training a machine learning model on a distributed computing system. The model can be trained using selected processors of the training platform. The distributed system automatically modifies the model for instantiation on each processor, adjusts an input pipeline to accommodate the capabilities of selected processors, and coordinates the training between those processors. Simultaneous processing at each stage can be scaled to reduce or eliminate bottlenecks in the distributed system. In addition, autonomous monitoring and re-allocating of resources can further reduce or eliminate bottlenecks. The training results may be aggregated by the distributed system, and a final model may then be transmitted to a user device.

The invention discloses an operation module, a pipeline optimization method, and a related product, which are applied to a combined processing device. The combined processing device comprises: electronic equipment, an interface device, other processing devices, and a storage device, wherein the electronic equipment can comprise one or more computing devices, and the computing devices can be configured to execute the pipeline optimization method. By adopting the embodiment of the invention, computing resources can be saved.

The invention provides a parallel pipeline computing device of CNC interpolation, which is characterized by comprising a parallel/pipeline computing member CU3B which is formed by a plurality of computing units CU3; and a data memory. The computing units CU3 comprise six adders, two shifters for right shifting 1 bit, two shifters for right shifting 2 bits and a shifter for right shifting 3 bits; four data output ends, namely, a beta 0l data output end, a beta 1l data output end, a beta 2l data output end and a beta 3l data output end of the former computing unit CU3 and four data output ends, namely, a beta 0r data output end, a beta 1r data output end, a beta 2r data output end and a beta 3r data output end are respectively connected with four data input ends, namely, a beta 0 data input end, a beta 1 data input end, a beta 2 data input end, and a beta 3 data input end of the next two computing units CU3, so that 2n-1 computing units CU3 form the parallel/pipeline computing member CU3B; the beta (0.5) data output end of each computing unit CU3 is connected with the data memory. Compared with the prior art, the device has high speed calculation and accurate results; the device is suitable for reconfigurable computation of chip level parallel pipeline and meets the developing industrial requirements.