2-D parity checkup correction method and its realization hardware based on advanced encryption standard

Abstract

The invention relates to a technical field of integrate circuit design, specifically to a two-dimension parity check error detecting method in an advanced encryption standard and an implement hardware thereof. The method, by performing a two-dimension parity check in a horizontal direction and a vertical orientation for the data in the advanced encryption standard, can completely covers the odd number errors by performing a two-dimension parity check in a horizontal direction and a vertical orientation for the data in the advanced encryption standard, has a skyhigh percentage of coverage for the even number errors, especially completely covers the two errors in the condition the number of the error is two, and is capable of effectively resisting error impact. The hardware for actualizing the invention uses a completely parallel construction between a principal operation module and a two-dimension parity check digit computation module, wherein, in the principal operation module, 128 bit data are divided into 4 groups of 32 bit data and uses 2-degree pipeline architecture, and the parity check digit computation module uses a 32 bit data computing mode. The hardware structure has no affect on the data throughput in the in an advanced encryption standard, the leading in extra hardware has a low cost, and the invention is fit for an application area with a high security requirement and a strict hardware area requirement.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to an advanced encryption standard anti-differential error attack-based concurrency error detection method and its hardware implementation. Background technique [0002] Differential error attack is a side-channel attack method that artificially introduces errors in the process of cryptographic algorithm hardware operations, and analyzes the results of multiple errors to obtain the key of the cryptographic algorithm. The method can decipher the key of the cryptographic algorithm in a relatively short time without causing any damage to the hardware of the cryptographic algorithm. [0003] One of the methods to effectively defend against differential error attacks is to add a concurrent error detection module during the operation of the cryptographic algorithm, among which the parity-based concurrent error detection is the most common. The traditional pa...

AI Technical Summary

Problems solved by technology

However, the main defect of these methods is that they can only detect parity errors in one direction, so although all odd-numbered errors can be detected, complete coverage cannot be achieved for even-numbered errors

Especially for the case of two errors, its error coverage is the lowest, which greatly affects the security of the hardware implementation of Advanced Encryption Standard

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