Efficient zero-knowledge proof accelerator and method

Abstract

The invention relates to an efficient zero-knowledge proof accelerator which can provide a high-computing-power and high-efficiency hardware carrier for zero-knowledge proof calculation. According to the method, a fine-grained pipeline architecture is adopted for multi-scalar multiplication, and a plurality of elliptic curve point addition architectures can be integrated into a large-number modular multiplication hardware circuit under the condition that the chip area is not increased, that is, pipeline calculation acceleration can be carried out on elliptic curve point addition calculation only through one large-number modular multiplication hardware circuit. Meanwhile, a plurality of large-number modular multiplication hardware circuits are further integrated, and parallel acceleration can be carried out on point addition calculation of a plurality of elliptic curves. Therefore, compared with the prior art, the method is more flexible and suitable for ASICs and FPGAs of different scales.

Description

Technical field [0001] This disclosure involves electronic information technology, which specifically involves an efficient scratch -knowledge proof accelerator and method. Background technique [0002] Zero Knowledge Proofs (ZKP) is a powerful cryptography protocol. In short, the answer to the questioner (Prover) knows the answer, he needs to prove the fact that "he knows the answer" is proved to the verification, but the verifier cannot obtain any information about the answer. At present, zero knowledge has proved that due to its high privacy and simplicity, it is particularly useful for providing privacy preservation. There are many applications in the blockchain field, such as secure multi -party calculations, distributed storage, can be verified outsourcing databases, chain expansion, online auction, and so on. However, an important obstacle in the application in the application is that the proof of the proof of the proof is very time -consuming, because the generating proof...

AI Technical Summary

Problems solved by technology

[0004]The existing technology adopts the ASIC of the pipeline architecture to realize the zero-knowledge proof accelerator, which internally realizes the acceleration of polynomial calculation and elliptic curve multi-scalar multiplication, but due to the elliptic The multi-scalar multiplication of curves is realized by the Pippenger algorithm and the coarse-grained pipeline architecture, which leads to the need for dozens of large-number analog multiplication hardware circuits inside the accelerator, which directly leads to the need for a large number of DSP units

Therefore, ASIC requires a large chip area, and an excessively large chip area can easily lead to an increase in the defective rate of chip mass production

However, if it is realized by FPGA, it is difficult to deploy such an ASIC with pipeline architecture on an FPGA chip with limited DSP resources.

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