Multi-parallel strategy convolutional network accelerator based on FPGA

Abstract

The invention discloses a multi-parallel strategy convolutional network accelerator based on an FPGA, and relates to the field of network computing. The system comprises a single-layer network computing structure, the single-layer network computing structure comprises a BN layer, a convolution layer, an activation layer and a pooling layer, the four layers of networks form an assembly line structure, and the BN layer merges input data; the convolution layer is used for carrying out a large amount of multiplication and additive operation, wherein the convolution layer comprises a first convolution layer, a middle convolution layer and a last convolution layer, and convolution operation is carried out by using one or more of input parallel, pixel parallel and output parallel; the activationlayer and the pooling layer are used for carrying out pipeline calculation on an output result of the convolution layer; and storing a pooled and activated final result into an RAM (Random Access Memory). Three parallel structures are combined, different degrees of parallelism can be configured at will, high flexibility is achieved, free combination is achieved, and high parallel processing efficiency is achieved.

Description

technical field [0001] The invention relates to the field of network computing, in particular to an FPGA-based multi-parallel policy convolution network accelerator. Background technique [0002] In recent years, deep learning has greatly accelerated the development of machine learning and artificial intelligence and has achieved remarkable results in various research fields and commercial applications. [0003] Field Programmable Gate Array (FPGA) is one of the preferred platforms for embedded implementation of deep learning algorithms. FPGA has low power consumption and a certain degree of parallelism, and FPGA focuses on solving real-time problems of algorithms. [0004] FPGA accelerators can be divided into fixed-point accelerators and floating-point accelerators. The fixed-point accelerator mainly designs parallel acceleration units for the convolution calculation process to achieve efficient convolution calculations. The floating-point accelerator also designs a par...

AI Technical Summary

Problems solved by technology

The calculation efficiency of floating-point accelerators is lower than that of fixed-point accelerators, and fixed-point accelerators often ignore the accuracy of fixed-point networks

In order to solve the problem of accuracy, the existing quantization methods are more inclined to software implementation, without considering the calculation characteristics of FGPA, the calculation complexity is high, and the implementation efficiency is low

[0005] In response to the above problems, the existing method is to propose Google (IAO), which uses the Integer Arithmetic Only (IAO) method to calculate and express the forward reasoning process of the network, which not only meets the calculation characteristics of the FPGA platform, but also ensures the accuracy of the network after quantization. But there is a computational redundancy problem

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