54results about How to "Reduce vacancy" patented technology

A manufacturing procedure control method. The method executes tests during transport for object lots. The object lots are carried on a transport vehicle during transport. The object lots that pass the tests are loaded in a manufacturing tool. If a load port and a tag reader are provided on the transport vehicle, additional tests can be performed during transport of the object lots.

A preparation method of epoxy phenolic nano-anticorrosion coating, which is prepared from component A and component B according to the following raw material mass percentages: (1) component A: 8-10% epoxy resin, 16-20% phenolic resin, 15-20% mixed solvent, 1-2% nanoparticles, 0.2-0.5% coupling agent, 5-8% zinc phosphate, 40-45% filler, 1.5-3% additives; (2) B component: 45 ~55% Versamine I‑70 type curing agent, 45~55% mixed solvent; the prepared component A and component B are mixed evenly according to the mass ratio of 10: (4~5) to make epoxy phenolic nano anticorrosion coating, The new nano-modified components introduced by the coating can reduce the gaps and vacancies between the coating molecules, make the coating more tightly bonded, and effectively improve the anti-corrosion performance of the coating.

The invention discloses an apparatus for the vertical pulling growth of CdZnTe monocrystals, and a method thereof. The apparatus comprises a tubular furnace body, a quartz ampoule and a graphite boat, the furnace body comprises synthetic furnaces, buffer furnaces, inclined plane furnaces and Cd source furnaces, the quartz ampoule is arranged in the furnace body, the graphite boat is arranged in the quartz ampoule. The method for the vertical pulling growth of CdZnTe monocrystals through adopting the apparatus generally comprises the following steps: uniformly putting a high-purity Te raw material, a high-purity Zn raw material and a high-purity Cd raw material in the graphite boat according to synthetic proportions, putting a small amount of Cd at the bottom of the quartz ampoule, slowly putting the graphite boat on the baffle board of the quartz ampoule, carrying out vacuumizing tube sealing, putting the quartz ampoule in the tubular furnace body to make the graphite boat in the middle of the synthetic furnaces, controlling conditions for synthesizing polycrystals, controlling the temperature distribution of the furnace body, slowly upward moving the furnace body until crystallization finishing, and carrying out vertical pulling growth to obtain the CdZnTe monocrystals. According to the invention, CdZnTe polycrystals are synthesized without using other rocking furnaces; and the obtained CdZnTe monocrystals have the advantages of uniform crystal ingot component, less twin crystals, and less Te precipitation or inclusions.

It is a method for manufacturing an electrode material containing Cu, Cr, a heat-resistant element, and a low melting metal. A Cr powder and a heat-resistant element powder are mixed together in a ratio such that the Cr is greater than the heat-resistant element by weight. The mixed powder of the heat-resistant element and the Cr powder is baked. A MoCr solid solution obtained by the baking and containing a solid solution of the heat-resistant element and the Cr is pulverized and then classified. The classified MoCr solid solution powder, a Cu powder, and a low-melting metal powder are mixed together, followed by sintering at a temperature that is 1010° C. or higher and is lower than 1038° C., thereby obtaining the electrode material.

A semiconductor structure and its forming method, wherein, the forming method includes: providing a substrate; forming a gate dielectric layer on the substrate; performing a ventilation treatment on the gate dielectric layer to form a modified gate dielectric layer; A work function layer is formed on the modified gate dielectric layer; a gate layer is formed on the work function layer. The ventilation treatment can make nitrogen atoms fill the vacancies and gaps in the gate dielectric layer, thereby preventing the metal atoms in the work function layer from diffusing into the gate dielectric layer, thereby reducing the change of the work function of the gate dielectric layer , thereby reducing the drift of the threshold voltage of the formed semiconductor structure, and reducing the instability of the bias voltage of the formed semiconductor structure.