35results about How to "Avoid etch residue" patented technology

The invention discloses a display panel and a manufacturing method thereof. The display panel comprises an array substrate, a plurality of reflecting electrodes, a plurality of isolation units, an anode layer and a light-emitting function layer. The plurality of reflecting electrodes are positioned on the array substrate and are distributed in an array manner; one isolation unit is arranged between any two adjacent reflecting electrodes; the anode layer comprises a first anode located on each reflecting electrode and a second anode located on the side, away from the array substrate, of each isolation unit, and each first anode and the adjacent second anode are spaced through the corresponding isolation unit; and the light-emitting function layer is located on the first anodes. According tothe invention, two adjacent first anodes can be naturally disconnected through the isolation unit, and the cavity length of the device can be adjusted through the thickness of the first anodes.

The invention provides an etching method, and the etching method comprises the steps: providing a substrate, and sequentially stacking a control gate layer, a floating gate layer, a first word line and a second word line on the substrate, wherein the first word line and the second word line penetrate through the control gate layer and the floating gate layer, the first word line is located in a logic region, and the second word line is located in a memory cell region; etching the first word line with the first thickness; etching the floating gate layer in the logic region and the first word line with the second thickness so as to expose the control gate layer in the logic region; and etching the control gate layer in the logic region and the first word line with the third thickness so as to remove the control gate layer in the logic region. In the logic region etching process, the first word line with the first thickness is etched firstly, and then the first word line, the floating gate layer and the control gate layer are etched synchronously, so that etching residues caused by the low etching rate of the first word line are avoided. Therefore, the etching method can solve the problem that etching residues are generated due to etching selection ratio, the process effect is guaranteed, and the process time is saved.

The invention provides a bulk acoustic wave resonator, a manufacturing method thereof, a filter and a radio frequency communication system. A bottom electrode concave part formed on the periphery of apiezoelectric resonance layer and suspended above a cavity can prevent transverse waves generated by the piezoelectric resonance layer from being transmitted to the periphery of the cavity and reflect the transverse waves back to an effective working area, so that the sound wave loss is reduced, the quality factor of the resonator is improved, and finally, the performance of a device can be improved. Furthermore, the overlapping parts of a bottom electrode overlapping part and the cavity and the overlapping parts of a top electrode overlapping part and the cavity are suspended, and the bottomelectrode overlapping part and the top electrode overlapping part are mutually staggered, so that a parasitic parameter can be greatly reduced, the problems of electric leakage, short circuit and thelike can be avoided, and the reliability of the device can be improved.

The invention discloses a manufacture method for a thin-film resistor. The manufacture method comprises the following steps that: S01: providing a substrate of which the surface is coated with an insulating layer; S02: depositing a thin film resistor material on the substrate, and carrying out graphics on the film resistor material; S03: depositing a metal electrode material, an etching stop layerand a hard mask in sequence on the substrate and the thin film resistor material; S04: adopting first-type dry method etching to carry out graphics on the hard mask, and removing photoresist; S05: adopting second-type dry method etching to continuously carry out graphics on the etching stop layer; and S06: adopting wet method etching to continuously carry out graphics on the metal electrode material to form the thin-film resistor. By use of the manufacture method, the problem of the over etching of the thin-film resistor and the etching residue of the metal electrode can be avoided, and the accuracy and the reliability of the thin-film resistor can be improved.

The present invention discloses a preparation method of a thin-film resistor. The method comprises the following steps: S01 providing a substrate, wherein the surface of the substrate is covered withan insulation layer; S02 depositing and graphing a thin-film resistor material layer on the substrate; S03 depositing a metal electrode material layer and a hard mask layer on the substrate and the thin-film resistor material layer successively; S04 graphing the hard mask layer by adopting dry etching, stopping on the metal electrode material layer, and removing the hard mask layer at the steps ofthe metal electrode material layer and the hard mask layer between the steps of the metal electrode material layer completely; S05 processing the surface of the exposed metal electrode material layerby adopting reducing gas(es); and S06 graphing the metal electrode material by adopting isotropic etching, and removing the exposed metal electrode material layer to form the thin-film resistor. Thepreparation method of the thin-film resistor can avoid the problems of over-etching of the thin-film resistor and etching residue of the metal electrode and improve the accuracy and the reliability ofthe thin-film resistor.

The invention discloses a TFT manufacturing method and a TFT substrate. In the process of etching to form a polysilicon pattern, one part of a polysilicon layer is covered by a non-hollowed region ofa photoresist pattern, the other part is exposed by a hollowed-out region of the photoresist pattern, secondly, dry etching of the polysilicon layer is carried out through employing the first etchinggas to remove protrusion of the polysilicon layer not covered by the photoresist pattern, and dry etching of the polysilicon layer is carried out through employing the second etching gas to remove thepart of the polysilicon layer not covered by the photoresist pattern. The method is advantaged in that complete etching can be facilitated to remove the polysilicon layer not covered by the photoresist pattern, and etching residue is avoided.

The invention provides a bulk acoustic wave resonator, a manufacturing method thereof, a filter and a radio frequency communication system. A top electrode protruding part formed on the periphery of apiezoelectric resonance layer and suspended above a cavity can prevent transverse waves generated by the piezoelectric resonance layer from being transmitted to the periphery of the cavity and reflect the transverse waves back to an effective working area, so that the sound wave loss is reduced, the quality factor of the resonator is improved, and finally the performance of a device can be improved. Furthermore, the overlapping parts of a bottom electrode overlapping part and the cavity and the overlapping parts of a top electrode overlapping part and the cavity are suspended, and the bottomelectrode overlapping part and the top electrode overlapping part are mutually staggered, so that a parasitic parameter can be greatly reduced, the problems of electric leakage, short circuit and thelike can be avoided, and the reliability of the device can be improved.

The invention relates to a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a base, wherein the base comprises a substrate and discrete fins arranged on the substrate in a protruding manner; forming a pseudo gate structure stretching across the fins, wherein the pseudo gate structure comprises a first pseudo gate layer and a second pseudo gate layer located on the first pseudo gate layer, the width of the first pseudo gate layer is gradually increased from bottom to top, and the side wall of the second pseudo gate layer is perpendicularto the top surface of the substrate; forming a source-drain doping layer in the fins on the two sides of the pseudo gate structure; forming a dielectric layer on the source-drain doping layer, whereinthe dielectric layer exposes the top of the pseudo gate structure; removing the pseudo gate structure, and forming an opening in the dielectric layer; and forming a metal gate structure filling the opening. The included angle between the side wall of the first pseudo gate layer and the top wall of the fin is less than 90 degrees, so that the process space for subsequently removing the first pseudo gate layer is large, and the first pseudo gate layer is not prone to being left. On the basis, the side wall of the second pseudo gate layer is perpendicular to the top surface of the substrate, sothat the transverse space of the top surface of the fin is saved, the further reduction of the device size is facilitated, and the performance of the semiconductor structure is optimized.